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Message-ID: <aXqD5JUmMJAiQU2C@aschofie-mobl2.lan>
Date: Wed, 28 Jan 2026 13:47:16 -0800
From: Alison Schofield <alison.schofield@...el.com>
To: "Koralahalli Channabasappa, Smita" <skoralah@....com>
CC: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>,
	<linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<nvdimm@...ts.linux.dev>, <linux-fsdevel@...r.kernel.org>,
	<linux-pm@...r.kernel.org>, Ard Biesheuvel <ardb@...nel.org>, Vishal Verma
	<vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>, Dan Williams
	<dan.j.williams@...el.com>, Jonathan Cameron <jonathan.cameron@...wei.com>,
	Yazen Ghannam <yazen.ghannam@....com>, Dave Jiang <dave.jiang@...el.com>,
	Davidlohr Bueso <dave@...olabs.net>, Matthew Wilcox <willy@...radead.org>,
	Jan Kara <jack@...e.cz>, "Rafael J . Wysocki" <rafael@...nel.org>, Len Brown
	<len.brown@...el.com>, Pavel Machek <pavel@...nel.org>, Li Ming
	<ming.li@...omail.com>, Jeff Johnson <jeff.johnson@....qualcomm.com>, "Ying
 Huang" <huang.ying.caritas@...il.com>, Yao Xingtao <yaoxt.fnst@...itsu.com>,
	Peter Zijlstra <peterz@...radead.org>, Greg Kroah-Hartman
	<gregkh@...uxfoundation.org>, Nathan Fontenot <nathan.fontenot@....com>,
	Terry Bowman <terry.bowman@....com>, Robert Richter <rrichter@....com>,
	Benjamin Cheatham <benjamin.cheatham@....com>, Zhijian Li
	<lizhijian@...itsu.com>, Borislav Petkov <bp@...en8.de>, Tomasz Wolski
	<tomasz.wolski@...itsu.com>
Subject: Re: [PATCH v5 6/7] dax/hmem, cxl: Defer and resolve ownership of
 Soft Reserved memory ranges

On Wed, Jan 28, 2026 at 01:14:52PM -0800, Koralahalli Channabasappa, Smita wrote:
> On 1/26/2026 5:38 PM, Alison Schofield wrote:
> 
> [snip]
> ..
> 
> > > +static void process_defer_work(struct work_struct *_work)
> > > +{
> > > +	struct dax_defer_work *work = container_of(_work, typeof(*work), work);
> > > +	struct platform_device *pdev = work->pdev;
> > > +	int rc;
> > > +
> > > +	/* relies on cxl_acpi and cxl_pci having had a chance to load */
> > > +	wait_for_device_probe();
> > > +
> > > +	rc = walk_hmem_resources(&pdev->dev, cxl_contains_soft_reserve);
> > > +
> > > +	if (!rc) {
> > > +		dax_cxl_mode = DAX_CXL_MODE_DROP;
> > > +		rc = bus_rescan_devices(&cxl_bus_type);
> > > +		if (rc)
> > > +			dev_warn(&pdev->dev, "CXL bus rescan failed: %d\n", rc);
> > > +	} else {
> > > +		dax_cxl_mode = DAX_CXL_MODE_REGISTER;
> > > +		cxl_region_teardown_all();
> > 
> > The region teardown appears as a one-shot sweep of existing regions
> > without considering regions not yet assembled. After this point will
> > a newly arriving region, be racing with HMEM again to create a DAX
> > region?
> 
> My understanding is that with the probe ordering patches and
> wait_for_device_probe(), CXL region discovery and assembly should have
> completed before this point.

OK - my confusion. Thanks for explaining.
-- Alison


> 
> Thanks
> Smita
> > 
> > 
> > > +	}
> > > +
> > > +	walk_hmem_resources(&pdev->dev, hmem_register_device);
> > > +}
> > > +
> > > +static void kill_defer_work(void *_work)
> > > +{
> > > +	struct dax_defer_work *work = container_of(_work, typeof(*work), work);
> > > +
> > > +	cancel_work_sync(&work->work);
> > > +	kfree(work);
> > > +}
> > > +
> > >   static int dax_hmem_platform_probe(struct platform_device *pdev)
> > >   {
> > > +	struct dax_defer_work *work = kzalloc(sizeof(*work), GFP_KERNEL);
> > > +	int rc;
> > > +
> > > +	if (!work)
> > > +		return -ENOMEM;
> > > +
> > > +	work->pdev = pdev;
> > > +	INIT_WORK(&work->work, process_defer_work);
> > > +
> > > +	rc = devm_add_action_or_reset(&pdev->dev, kill_defer_work, work);
> > > +	if (rc)
> > > +		return rc;
> > > +
> > > +	platform_set_drvdata(pdev, work);
> > > +
> > >   	return walk_hmem_resources(&pdev->dev, hmem_register_device);
> > >   }
> > > @@ -174,3 +250,4 @@ MODULE_ALIAS("platform:hmem_platform*");
> > >   MODULE_DESCRIPTION("HMEM DAX: direct access to 'specific purpose' memory");
> > >   MODULE_LICENSE("GPL v2");
> > >   MODULE_AUTHOR("Intel Corporation");
> > > +MODULE_IMPORT_NS("CXL");
> > > -- 
> > > 2.17.1
> > > 
> 

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