linux-kernel - Re: [PATCH 1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports

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Message-ID: <176959816683.2069840.8945134159377635375.b4-ty@kernel.org>
Date: Wed, 28 Jan 2026 12:04:04 +0100
From: "Christophe Leroy (CS GROUP)" <chleroy@...nel.org>
To: Qiang Zhao <qiang.zhao@....com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	"Christophe Leroy (CS GROUP)" <chleroy@...nel.org>
Cc: linuxppc-dev@...ts.ozlabs.org,
	linux-arm-kernel@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports


On Wed, 07 Jan 2026 17:59:09 +0100, Christophe Leroy (CS GROUP) wrote:
> The QUICC Engine provides interrupts for a few I/O ports. This is
> handled via a separate interrupt ID and managed via a triplet of
> dedicated registers hosted by the SoC.
> 
> Implement an interrupt driver for it so that those IRQs can then
> be linked to the related GPIOs.
> 
> [...]

Applied, thanks!

[1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
[2/2] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports

Best regards,
-- 
Christophe Leroy (CS GROUP) <chleroy@...nel.org>