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Message-ID: <20260128113032.337231-1-biju.das.jz@bp.renesas.com>
Date: Wed, 28 Jan 2026 11:30:19 +0000
From: Biju <biju.das.au@...il.com>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Vinod Koul <vkoul@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-kernel@...r.kernel.org,
linux-serial@...r.kernel.org,
dmaengine@...r.kernel.org,
devicetree@...r.kernel.org,
linux-clk@...r.kernel.org,
linux-renesas-soc@...r.kernel.org,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>
Subject: [PATCH v2 00/10] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform
From: Biju Das <biju.das.jz@...renesas.com>
Hi all,
This patch series adds initial support for the Renesas RZ/G3L SoC and
RZ/G3L SMARC EVK platform. The RZ/G3L device is a general-purpose
microprocessor with a quad-core CA-55, single core CM-33, Mali-G31
3-D Graphics and other peripherals.
Support for the below list of blocks is added in the SoC DTSI (r9a08g046.dtsi):
- EXT CLK
- 4X CA55
- SCIF
- CPG
- GIC
- ARMv8 Timer
This series also adds SCIF support for the RZ/G3L SMARC EVK board (r9a08g046l48-smarc.dts).
v1->v2:
* Dropped scif bindings patch as it is accepted.
* Collected tags.
* Squashed the patch#3 and #4
* Documented GE3D/VCP for all SoC variants
* Documented external ethernet clocks as it is a clock source for MUX
inside CPG
* Updated commit description for bindings.
* Keep the tag from Conor as it is trivial change for adding more
clks.
* Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks
in clk table.
* Dropped R9A08G046_IA55_PCLK from critical clock list.
* Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk
in soc dtsi as it needed for cpg as it is a clock source for mux.
* Updated cpg node.
* Dropped gpio.h header from SoM dtsi.
* Dropped scif node as it is already included in common platform
file.
Test logs:
/ #uname -r
6.19.0-rc7-next-20260127-g6e9651049dd7
/ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 2
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 3
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
/ # cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 356 1051 444 127 GICv3 27 Level arch_timer
14: 0 0 0 0 GICv3 185 Edge error
15: 0 0 0 0 GICv3 186 Edge 11820000.dma-controller:0
16: 0 0 0 0 GICv3 187 Edge 11820000.dma-controller:1
17: 0 0 0 0 GICv3 188 Edge 11820000.dma-controller:2
18: 0 0 0 0 GICv3 189 Edge 11820000.dma-controller:3
19: 0 0 0 0 GICv3 190 Edge 11820000.dma-controller:4
20: 0 0 0 0 GICv3 191 Edge 11820000.dma-controller:5
21: 0 0 0 0 GICv3 192 Edge 11820000.dma-controller:6
22: 0 0 0 0 GICv3 193 Edge 11820000.dma-controller:7
23: 0 0 0 0 GICv3 194 Edge 11820000.dma-controller:8
24: 0 0 0 0 GICv3 195 Edge 11820000.dma-controller:9
25: 0 0 0 0 GICv3 196 Edge 11820000.dma-controller:10
26: 0 0 0 0 GICv3 197 Edge 11820000.dma-controller:11
27: 0 0 0 0 GICv3 198 Edge 11820000.dma-controller:12
28: 0 0 0 0 GICv3 199 Edge 11820000.dma-controller:13
29: 0 0 0 0 GICv3 200 Edge 11820000.dma-controller:14
30: 0 0 0 0 GICv3 201 Edge 11820000.dma-controller:15
31: 0 0 0 0 GICv3 418 Level 100ac000.serial:rx err
32: 3 0 0 0 GICv3 420 Level 100ac000.serial:rx full
33: 259 0 0 0 GICv3 421 Level 100ac000.serial:tx empty
34: 0 0 0 0 GICv3 419 Level 100ac000.serial:break
35: 26 0 0 0 GICv3 422 Level 100ac000.serial:rx ready
IPI0: 18 32 21 19 Rescheduling interrupts
IPI1: 269 367 204 122 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop NMIs
IPI4: 0 0 0 0 Timer broadcast interrupts
IPI5: 0 0 0 0 IRQ work interrupts
IPI6: 0 0 0 0 CPU backtrace interrupts
IPI7: 0 0 0 0 KGDB roundup interrupts
Err: 0
/ # cat /proc/meminfo
MemTotal: 1887812 kB
MemFree: 1849032 kB
MemAvailable: 1816456 kB
/ # cat /sys/devices/soc0/family
RZ/G3L
/ # cat /sys/devices/soc0/machine
Renesas SMARC EVK version 2 based on r9a08g046l48
/ # cat /sys/devices/soc0/soc_id
r9a08g046
/ # cat /sys/devices/soc0/revision
0
Biju Das (10):
dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and
Carrier-II EVK
dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoC
dt-bindings: clock: Document RZ/G3L SoC
clk: renesas: Add support for RZ/G3L SoC
arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK
board
.../bindings/clock/renesas,rzg2l-cpg.yaml | 40 ++-
.../bindings/dma/renesas,rz-dmac.yaml | 1 +
.../soc/renesas/renesas,rzg2l-sysc.yaml | 1 +
.../bindings/soc/renesas/renesas.yaml | 13 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 251 +++++++++++++
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 37 ++
arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 +
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 6 +
.../boot/dts/renesas/renesas-smarc2.dtsi | 8 -
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 20 ++
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a08g046-cpg.c | 144 ++++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 1 +
drivers/soc/renesas/Kconfig | 12 +
drivers/soc/renesas/Makefile | 1 +
drivers/soc/renesas/r9a08g046-sysc.c | 91 +++++
drivers/soc/renesas/rz-sysc.c | 3 +
drivers/soc/renesas/rz-sysc.h | 1 +
include/dt-bindings/clock/r9a08g046-cpg.h | 339 ++++++++++++++++++
22 files changed, 984 insertions(+), 14 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c
create mode 100644 drivers/soc/renesas/r9a08g046-sysc.c
create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h
--
2.43.0
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