| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20260129191607.axkkrion3zakb7pg@offworld>
Date: Thu, 29 Jan 2026 11:16:07 -0800
From: Davidlohr Bueso <dave@...olabs.net>
To: Gregory Price <gourry@...rry.net>
Cc: linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
kernel-team@...a.com, jonathan.cameron@...wei.com,
dave.jiang@...el.com, alison.schofield@...el.com,
vishal.l.verma@...el.com, ira.weiny@...el.com,
dan.j.williams@...el.com, anisa.su@...sung.com,
dongjoo.seo1@...sung.com, s.neeraj@...sung.com
Subject: Re: [PATCH v2 3/3] cxl/core/region: move dax region driver logic
into dax_region
On Tue, 13 Jan 2026, Gregory Price wrote:
>Move the dax region driver logic from region.c into dax_region.c
>
>Signed-off-by: Gregory Price <gourry@...rry.net>
Acked-by: Davidlohr Bueso <dave@...olabs.net>
>---
> drivers/cxl/core/Makefile | 1 +
> drivers/cxl/core/core.h | 1 +
> drivers/cxl/core/dax_region.c | 106 ++++++++++++++++++++++++++++++++++
> drivers/cxl/core/region.c | 99 -------------------------------
> 4 files changed, 108 insertions(+), 99 deletions(-)
> create mode 100644 drivers/cxl/core/dax_region.c
>
>diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
>index 23269c81fd44..36f284d7c500 100644
>--- a/drivers/cxl/core/Makefile
>+++ b/drivers/cxl/core/Makefile
>@@ -17,6 +17,7 @@ cxl_core-y += cdat.o
> cxl_core-y += ras.o
> cxl_core-$(CONFIG_TRACING) += trace.o
> cxl_core-$(CONFIG_CXL_REGION) += region.o
>+cxl_core-$(CONFIG_CXL_REGION) += dax_region.o
> cxl_core-$(CONFIG_CXL_REGION) += pmem_region.o
> cxl_core-$(CONFIG_CXL_MCE) += mce.o
> cxl_core-$(CONFIG_CXL_FEATURES) += features.o
>diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
>index cd589e81f55e..3ea850408814 100644
>--- a/drivers/cxl/core/core.h
>+++ b/drivers/cxl/core/core.h
>@@ -42,6 +42,7 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port);
> struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
> u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
> u64 dpa);
>+int devm_cxl_add_dax_region(struct cxl_region *cxlr);
> int devm_cxl_add_pmem_region(struct cxl_region *cxlr);
>
> #else
>diff --git a/drivers/cxl/core/dax_region.c b/drivers/cxl/core/dax_region.c
>new file mode 100644
>index 000000000000..d7c38447f816
>--- /dev/null
>+++ b/drivers/cxl/core/dax_region.c
>@@ -0,0 +1,106 @@
>+// SPDX-License-Identifier: GPL-2.0-only
>+/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
>+#include <linux/device.h>
>+#include <linux/slab.h>
>+#include <cxlmem.h>
>+#include <cxl.h>
>+#include "core.h"
>+
>+static void cxl_dax_region_release(struct device *dev)
>+{
>+ struct cxl_dax_region *cxlr_dax = to_cxl_dax_region(dev);
>+
>+ kfree(cxlr_dax);
>+}
>+
>+static const struct attribute_group *cxl_dax_region_attribute_groups[] = {
>+ &cxl_base_attribute_group,
>+ NULL,
>+};
>+
>+const struct device_type cxl_dax_region_type = {
>+ .name = "cxl_dax_region",
>+ .release = cxl_dax_region_release,
>+ .groups = cxl_dax_region_attribute_groups,
>+};
>+
>+static bool is_cxl_dax_region(struct device *dev)
>+{
>+ return dev->type == &cxl_dax_region_type;
>+}
>+
>+struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
>+{
>+ if (dev_WARN_ONCE(dev, !is_cxl_dax_region(dev),
>+ "not a cxl_dax_region device\n"))
>+ return NULL;
>+ return container_of(dev, struct cxl_dax_region, dev);
>+}
>+EXPORT_SYMBOL_NS_GPL(to_cxl_dax_region, "CXL");
>+
>+static struct lock_class_key cxl_dax_region_key;
>+
>+static struct cxl_dax_region *cxl_dax_region_alloc(struct cxl_region *cxlr)
>+{
>+ struct cxl_region_params *p = &cxlr->params;
>+ struct cxl_dax_region *cxlr_dax;
>+ struct device *dev;
>+
>+ guard(rwsem_read)(&cxl_rwsem.region);
>+ if (p->state != CXL_CONFIG_COMMIT)
>+ return ERR_PTR(-ENXIO);
>+
>+ cxlr_dax = kzalloc(sizeof(*cxlr_dax), GFP_KERNEL);
>+ if (!cxlr_dax)
>+ return ERR_PTR(-ENOMEM);
>+
>+ cxlr_dax->hpa_range.start = p->res->start;
>+ cxlr_dax->hpa_range.end = p->res->end;
>+
>+ dev = &cxlr_dax->dev;
>+ cxlr_dax->cxlr = cxlr;
>+ device_initialize(dev);
>+ lockdep_set_class(&dev->mutex, &cxl_dax_region_key);
>+ device_set_pm_not_required(dev);
>+ dev->parent = &cxlr->dev;
>+ dev->bus = &cxl_bus_type;
>+ dev->type = &cxl_dax_region_type;
>+
>+ return cxlr_dax;
>+}
>+
>+static void cxlr_dax_unregister(void *_cxlr_dax)
>+{
>+ struct cxl_dax_region *cxlr_dax = _cxlr_dax;
>+
>+ device_unregister(&cxlr_dax->dev);
>+}
>+
>+int devm_cxl_add_dax_region(struct cxl_region *cxlr)
>+{
>+ struct cxl_dax_region *cxlr_dax;
>+ struct device *dev;
>+ int rc;
>+
>+ cxlr_dax = cxl_dax_region_alloc(cxlr);
>+ if (IS_ERR(cxlr_dax))
>+ return PTR_ERR(cxlr_dax);
>+
>+ dev = &cxlr_dax->dev;
>+ rc = dev_set_name(dev, "dax_region%d", cxlr->id);
>+ if (rc)
>+ goto err;
>+
>+ rc = device_add(dev);
>+ if (rc)
>+ goto err;
>+
>+ dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent),
>+ dev_name(dev));
>+
>+ return devm_add_action_or_reset(&cxlr->dev, cxlr_dax_unregister,
>+ cxlr_dax);
>+err:
>+ put_device(dev);
>+ return rc;
>+}
>diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
>index a61805542b56..1ca5f5b02b22 100644
>--- a/drivers/cxl/core/region.c
>+++ b/drivers/cxl/core/region.c
>@@ -3239,105 +3239,6 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset,
> return -ENXIO;
> }
>
>-static void cxl_dax_region_release(struct device *dev)
>-{
>- struct cxl_dax_region *cxlr_dax = to_cxl_dax_region(dev);
>-
>- kfree(cxlr_dax);
>-}
>-
>-static const struct attribute_group *cxl_dax_region_attribute_groups[] = {
>- &cxl_base_attribute_group,
>- NULL,
>-};
>-
>-const struct device_type cxl_dax_region_type = {
>- .name = "cxl_dax_region",
>- .release = cxl_dax_region_release,
>- .groups = cxl_dax_region_attribute_groups,
>-};
>-
>-static bool is_cxl_dax_region(struct device *dev)
>-{
>- return dev->type == &cxl_dax_region_type;
>-}
>-
>-struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
>-{
>- if (dev_WARN_ONCE(dev, !is_cxl_dax_region(dev),
>- "not a cxl_dax_region device\n"))
>- return NULL;
>- return container_of(dev, struct cxl_dax_region, dev);
>-}
>-EXPORT_SYMBOL_NS_GPL(to_cxl_dax_region, "CXL");
>-
>-static struct lock_class_key cxl_dax_region_key;
>-
>-static struct cxl_dax_region *cxl_dax_region_alloc(struct cxl_region *cxlr)
>-{
>- struct cxl_region_params *p = &cxlr->params;
>- struct cxl_dax_region *cxlr_dax;
>- struct device *dev;
>-
>- guard(rwsem_read)(&cxl_rwsem.region);
>- if (p->state != CXL_CONFIG_COMMIT)
>- return ERR_PTR(-ENXIO);
>-
>- cxlr_dax = kzalloc(sizeof(*cxlr_dax), GFP_KERNEL);
>- if (!cxlr_dax)
>- return ERR_PTR(-ENOMEM);
>-
>- cxlr_dax->hpa_range.start = p->res->start;
>- cxlr_dax->hpa_range.end = p->res->end;
>-
>- dev = &cxlr_dax->dev;
>- cxlr_dax->cxlr = cxlr;
>- device_initialize(dev);
>- lockdep_set_class(&dev->mutex, &cxl_dax_region_key);
>- device_set_pm_not_required(dev);
>- dev->parent = &cxlr->dev;
>- dev->bus = &cxl_bus_type;
>- dev->type = &cxl_dax_region_type;
>-
>- return cxlr_dax;
>-}
>-
>-static void cxlr_dax_unregister(void *_cxlr_dax)
>-{
>- struct cxl_dax_region *cxlr_dax = _cxlr_dax;
>-
>- device_unregister(&cxlr_dax->dev);
>-}
>-
>-static int devm_cxl_add_dax_region(struct cxl_region *cxlr)
>-{
>- struct cxl_dax_region *cxlr_dax;
>- struct device *dev;
>- int rc;
>-
>- cxlr_dax = cxl_dax_region_alloc(cxlr);
>- if (IS_ERR(cxlr_dax))
>- return PTR_ERR(cxlr_dax);
>-
>- dev = &cxlr_dax->dev;
>- rc = dev_set_name(dev, "dax_region%d", cxlr->id);
>- if (rc)
>- goto err;
>-
>- rc = device_add(dev);
>- if (rc)
>- goto err;
>-
>- dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent),
>- dev_name(dev));
>-
>- return devm_add_action_or_reset(&cxlr->dev, cxlr_dax_unregister,
>- cxlr_dax);
>-err:
>- put_device(dev);
>- return rc;
>-}
>-
> static int match_decoder_by_range(struct device *dev, const void *data)
> {
> const struct range *r1, *r2 = data;
>--
>2.52.0
>
Powered by blists - more mailing lists