linux-kernel - Re: [PATCH v4 14/15] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <87sebojk3d.fsf@bootlin.com>
Date: Thu, 29 Jan 2026 20:27:02 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Mark Brown <broonie@...nel.org>,  Rob Herring <robh@...nel.org>,
  Krzysztof Kozlowski <krzk+dt@...nel.org>,  Conor Dooley
 <conor+dt@...nel.org>,  Geert Uytterhoeven <geert+renesas@...der.be>,
  Magnus Damm <magnus.damm@...il.com>,  Vaishnav Achath
 <vaishnav.a@...com>,  Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
  Hervé Codina <herve.codina@...tlin.com>,  Wolfram Sang
 <wsa+renesas@...g-engineering.com>,  Vignesh Raghavendra
 <vigneshr@...com>,  Santhosh Kumar K <s-k6@...com>,  Pratyush Yadav
 <pratyush@...nel.org>,  Pascal Eberhard <pascal.eberhard@...com>,
  linux-spi@...r.kernel.org,  devicetree@...r.kernel.org,
  linux-kernel@...r.kernel.org,  linux-renesas-soc@...r.kernel.org
Subject: Re: [PATCH v4 14/15] spi: cadence-qspi: Add support for the Renesas
 RZ/N1 controller

On 29/01/2026 at 14:44:36 +01, Geert Uytterhoeven <geert@...ux-m68k.org> wrote:

> Hi Miquèl,
>
> Thanks for your patch!
>
> On Thu, 22 Jan 2026 at 16:14, Miquel Raynal (Schneider Electric)
> <miquel.raynal@...tlin.com> wrote:
>> Renesas RZ/N1 QSPI controllers embed a modified version of the Cadence
>> IP with the following settings:
>> - a limited bus clock range
>> - no DTR support
>> - no DMA
>> - no useful interrupt flag
>> - only direct accesses (no INDAC mode)
>> - write protection
>>
>> The controller has been tested by running the SPI NOR check list with a
>> custom RZ/N1D400 based board mounted with a Spansion s25fl128s1 quad
>
> "RZN1D-DB"?

I am indeed talking about the RZ/N1D400 here which is the "nice"
official name of the SoC. The board I was using is a custom board, not
the publicly available DB.

>
>> SPI.
>>
>> Tested-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
>> Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@...tlin.com>
>
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -110,6 +110,7 @@ struct cqspi_st {
>>         bool                    apb_ahb_hazard;
>>
>>         bool                    is_jh7110; /* Flag for StarFive JH7110 SoC */
>> +       bool                    is_rzn1; /* Flag for Renesas RZN1 SoC */
>
> RZ/N1

Crap :-) I will rebase the two patches Mark couldn't apply and add this
typo fix as a follow-up.

Thanks,
Miquèl