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Message-ID: <CA+V-a8trA53J5xt-p1odHkqeHgk_qXKQeXsf-QOfz2=JmTOSYA@mail.gmail.com>
Date: Thu, 29 Jan 2026 21:24:02 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Thomas Gleixner <tglx@...nel.org>
Cc: Philipp Zabel <p.zabel@...gutronix.de>, Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>, linux-kernel@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 4/6] irqchip/renesas-rzv2h: Add CA55 software interrupt support
Hi Thomas,
Thank you for the feedback.
On Mon, Jan 26, 2026 at 4:03 PM Thomas Gleixner <tglx@...nel.org> wrote:
>
> On Wed, Jan 21 2026 at 15:01, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > The Renesas RZ/V2H ICU provides a software interrupt register (ICU_SWINT)
> > that allows software to explicitly assert interrupts toward individual
> > CA55 cores. Writing BIT(n) to ICU_SWINT triggers the corresponding
> > interrupt.
> >
> > Introduce a debug mechanism to trigger software interrupts on individual
> > Cortex-A55 cores via the RZ/V2H ICU. The interface is gated behind
> > CONFIG_DEBUG_FS and a module parameter to ensure it only exists when
> > explicitly enabled.
>
> Can't you reuse/extend the existing mechanism provided by
> CONFIG_GENERIC_IRQ_INJECTION (irq_inject_interrupt(), irq_debug_write())
> instead of implementing yet another ad hoc debugfs magic?
>
Can you please point me to a driver which makes use of it? In my case
the interrupt needs to be triggered when BIT(n) (n=0-3) is written to
ICU_SWINT.
Cheers,
Prabhakar
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