linux-kernel - Re: [PATCH] pmdomain: imx: Fix i.MX8MP VPU

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Message-ID: <aXrQzt5YH5mP8RVF@shlinux89>
Date: Thu, 29 Jan 2026 11:15:26 +0800
From: Peng Fan <peng.fan@....nxp.com>
To: Frank Li <Frank.li@....com>
Cc: Ulf Hansson <ulf.hansson@...aro.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Lucas Stach <l.stach@...gutronix.de>, Jacky Bai <ping.bai@....com>,
	linux-pm@...r.kernel.org, imx@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Peng Fan <peng.fan@....com>, stable@...r.kernel.org
Subject: Re: [PATCH] pmdomain: imx: Fix i.MX8MP VPU_H1 power up sequence

On Wed, Jan 28, 2026 at 01:03:05PM -0500, Frank Li wrote:
>On Wed, Jan 28, 2026 at 11:11:25PM +0800, Peng Fan (OSS) wrote:
>> From: Peng Fan <peng.fan@....com>
>>
>
>Subject need descript what did
>
>for example:
>	fix build warning =>
>	do what to fix build warning.
>
>suggest
>	"Clear clk before power up gpc to implement workaroud of i.MX8MP errata"
>
>> Per errata:
>
>Provide errata link here

Sure. BTW, I also need to correct subject title to VC8000E.

Wait to see whether Lucas has any comments, then post out V2.

Thanks
Peng

>
>> ERR050531: VPU_NOC power down handshake may hang during VC8000E/VPUMIX
>> power up/down cycling.
>> Description: VC8000E reset de-assertion edge and AXI clock may have a
>> timing issue.
>> Workaround: Set bit2 (vc8000e_clk_en) of BLK_CLK_EN_CSR to 0 to gate off
>> both AXI clock and VC8000E clock sent to VC8000E and AXI clock sent to
>> VPU_NOC m_v_2 interface during VC8000E power up(VC8000E reset is
>> de-asserted by HW)
>>
>> Add a bool variable is_errata_err050531 in
>> 'struct imx8m_blk_ctrl_domain_data' to represent whether the workaround
>> is needed. If is_errata_err050531 is true, first clear the clk before
>> powering up gpc, then enable the clk after powering up gpc.
>>
>> While at here, using imx8mm_vpu_power_notifier() is wrong, as it ungates
>> the VPU clocks to provide the ADB clock, which is necessary on i.MX8MM,
>> but on i.MX8MP there is a separate gate (bit 3) for the NoC. So add
>> imx8mp_vpu_power_notifier() for i.MX8MP.
>>
>> Fixes: a1a5f15f7f6cb ("soc: imx: imx8m-blk-ctrl: add i.MX8MP VPU blk ctrl")
>> Cc: stable@...r.kernel.org
>> Signed-off-by: Peng Fan <peng.fan@....com>
>> ---
>>  drivers/pmdomain/imx/imx8m-blk-ctrl.c | 37 +++++++++++++++++++++++++++++++++--
>>  1 file changed, 35 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/pmdomain/imx/imx8m-blk-ctrl.c b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
>> index 74bf4936991d7c36346797d8b646dad40085fc2d..5b26b7c2c43172817d5e407a7d85eb6c5400d5a8 100644
>> --- a/drivers/pmdomain/imx/imx8m-blk-ctrl.c
>> +++ b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
>> @@ -54,6 +54,7 @@ struct imx8m_blk_ctrl_domain_data {
>>  	 * register.
>>  	 */
>>  	u32 mipi_phy_rst_mask;
>> +	bool is_errata_err050531;
>
>Put errata descritpion as comments here.
>
>>  };
>>
>>  #define DOMAIN_MAX_CLKS 4
>> @@ -108,7 +109,11 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
>>  		dev_err(bc->dev, "failed to enable clocks\n");
>>  		goto bus_put;
>>  	}
>> -	regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
>> +
>> +	if (data->is_errata_err050531)
>> +		regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
>> +	else
>> +		regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
>>
>>  	/* power up upstream GPC domain */
>>  	ret = pm_runtime_get_sync(domain->power_dev);
>> @@ -117,6 +122,9 @@ static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)
>>  		goto clk_disable;
>>  	}
>>
>> +	if (data->is_errata_err050531)
>> +		regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);
>> +
>>  	/* wait for reset to propagate */
>>  	udelay(5);
>>
>> @@ -514,9 +522,34 @@ static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[]
>>  	},
>>  };
>>
>> +static int imx8mp_vpu_power_notifier(struct notifier_block *nb,
>> +				     unsigned long action, void *data)
>> +{
>> +	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
>> +						 power_nb);
>> +
>> +	if (action == GENPD_NOTIFY_ON) {
>> +		/*
>> +		 * On power up we have no software backchannel to the GPC to
>> +		 * wait for the ADB handshake to happen, so we just delay for a
>> +		 * bit. On power down the GPC driver waits for the handshake.
>> +		 */
>> +
>> +		udelay(5);
>
>this time quite short, suggest read register before udelay() because udelay()
>is not neccesary to have MMIO read/write.
>
>Frank
>> +
>> +		/* set "fuse" bits to enable the VPUs */
>> +		regmap_set_bits(bc->regmap, 0x8, 0xffffffff);
>> +		regmap_set_bits(bc->regmap, 0xc, 0xffffffff);
>> +		regmap_set_bits(bc->regmap, 0x10, 0xffffffff);
>> +		regmap_set_bits(bc->regmap, 0x14, 0xffffffff);
>> +	}
>> +
>> +	return NOTIFY_OK;
>> +}
>> +
>>  static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = {
>>  	.max_reg = 0x18,
>> -	.power_notifier_fn = imx8mm_vpu_power_notifier,
>> +	.power_notifier_fn = imx8mp_vpu_power_notifier,
>>  	.domains = imx8mp_vpu_blk_ctl_domain_data,
>>  	.num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data),
>>  };
>>
>> ---
>> base-commit: 4f938c7d3b25d87b356af4106c2682caf8c835a2
>> change-id: 20260128-imx8mp-vc8000e-pm-4278e6d48b54
>>
>> Best regards,
>> --
>> Peng Fan <peng.fan@....com>
>>