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Message-ID: <45e1c870-f155-4943-990d-5e75a1e8b998@oss.qualcomm.com>
Date: Thu, 29 Jan 2026 10:57:29 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Jingoo Han <jingoohan1@...il.com>,
Manivannan Sadhasivam <mani@...nel.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kwilczynski@...nel.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Will Deacon <will@...nel.org>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
jonathanh@...dia.com
Subject: Re: [PATCH 3/3] PCI: qcom: Add D3cold support
On 1/28/2026 5:58 PM, Konrad Dybcio wrote:
> On 1/28/26 12:40 PM, Krishna Chaitanya Chundru wrote:
>> Add pme_turn_off() support and use DWC common suspend resume methods
>> for device D3cold entry & exit. If the device is not kept in D3cold
>> use existing methods like keeping icc votes, opp votes etc.. intact.
>>
>> In qcom_pcie_deinit_2_7_0(), explicitly disable PCIe clocks and resets
>> in the controller.
>>
>> Remove suspended flag from qcom_pcie structure as it is no longer needed.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
>> ---
> [...]
>
>> + /*
>> + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.
>> + * Because on some platforms, DBI access can happen very late during the
>> + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC
>> + * error.
>> + */
> I think someone internally once tracked down what that access was
As per last debug which I have done few years back we see access coming
IRQ driver to mask the interrupts
as part of disabling non boot CPU's.
> Can we fix that instead?
The only proper fix is to keep device in D3cold which this patch is
doing. if some client drivers like NVMe
doesn't want to go D3cold we need to honor it, but Mani is working on it
to allow NVMe drivers to go to D3cold.
- Krishna Chaitanya.
>
> Konrad
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