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Message-ID: <4eb3faa2c627a5a0f51a066a7810595ef856c74d.1769789834.git.tommaso.merciai.xr@bp.renesas.com>
Date: Fri, 30 Jan 2026 18:25:16 +0100
From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
To: tomm.merciai@...il.com,
geert@...ux-m68k.org,
laurent.pinchart@...asonboard.com
Cc: linux-renesas-soc@...r.kernel.org,
biju.das.jz@...renesas.com,
Tommaso Merciai <tommaso.merciai.xr@...renesas.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCH v2 19/20] arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes
Add DU0, DU1, DSI nodes to RZ/RZG3E SoC DTSI.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
---
v1->v2:
- Use single compatible string instead of multiple compatible strings
for the two DU instances, leveraging a 'renesas,id' property to
differentiate between DU0 and DU1.
- Use vclk instead of vclk1 for DSI Node and set to the right position.
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 123 +++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index d4db44b6ccf7..46240a6ff992 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -1432,6 +1432,129 @@ csi2cru: endpoint@0 {
};
};
+ dsi: dsi@...30000 {
+ compatible = "renesas,r9a09g047-mipi-dsi";
+ reg = <0 0x16430000 0 0x20000>;
+ interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "seq0", "seq1", "vin1", "rcv",
+ "ferr", "ppi", "debug";
+ clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>,
+ <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>,
+ <&cpg CPG_MOD 0x190>, <&cpg CPG_MOD 0xeb>;
+ clock-names = "pllrefclk", "aclk", "pclk", "vclk",
+ "lpclk", "vclk2";
+ resets = <&cpg 0xd8>, <&cpg 0xd7>;
+ reset-names = "arst", "prst";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in0: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_in1: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dsi_out: endpoint {
+ };
+ };
+ };
+ };
+
+ du0: display@...60000 {
+ compatible = "renesas,r9a09g047-du";
+ reg = <0 0x16460000 0 0x10000>;
+ interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0xed>,
+ <&cpg CPG_MOD 0xee>,
+ <&cpg CPG_MOD 0xef>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0xdc>;
+ renesas,vsps = <&vspd0 0>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du0_out_dsi0: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du0_out_lvds0: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ du0_out_lvds1: endpoint {
+ };
+ };
+ };
+ };
+
+ du1: display@...90000 {
+ compatible = "renesas,r9a09g047-du";
+ reg = <0 0x16490000 0 0x10000>;
+ interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 0x1a8>,
+ <&cpg CPG_MOD 0x1a9>,
+ <&cpg CPG_MOD 0x1aa>;
+ clock-names = "aclk", "pclk", "vclk";
+ power-domains = <&cpg>;
+ resets = <&cpg 0x11e>;
+ renesas,vsps = <&vspd1 0>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ du1_out_dsi0: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ du1_out_lvds0: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ du1_out_rgb0: endpoint {
+ };
+ };
+
+ };
+ };
+
fcpvd0: fcp@...70000 {
compatible = "renesas,r9a09g047-fcpvd",
"renesas,fcpv";
--
2.43.0
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