linux-kernel - Re: [PATCH v5 3/3] PCI: dwc: ep: Add comment explaining controller-level PTM access

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <aXzu05DSpiIgWSB4@lizhi-Precision-Tower-5810>
Date: Fri, 30 Jan 2026 12:48:03 -0500
From: Frank Li <Frank.li@....com>
To: Aksh Garg <a-garg7@...com>
Cc: linux-pci@...r.kernel.org, jingoohan1@...il.com, mani@...nel.org,
	lpieralisi@...nel.org, kwilczynski@...nel.org, robh@...nel.org,
	bhelgaas@...gle.com, cassel@...nel.org, Zhiqiang.Hou@....com,
	gustavo.pimentel@...opsys.com, den@...inux.co.jp,
	linux-kernel@...r.kernel.org, s-vadapalli@...com,
	danishanwar@...com
Subject: Re: [PATCH v5 3/3] PCI: dwc: ep: Add comment explaining
 controller-level PTM access

On Fri, Jan 30, 2026 at 05:25:16PM +0530, Aksh Garg wrote:
> PCIe r6.0, section 7.9.15 requires PTM capability in exactly one
> function to control all PTM-capable functions. This makes PTM registers
> controller-level rather than per-function.
>
> Add a comment explaining why PTM capability registers are accessed
> using the standard DBI accessors instead of func_no indexed
> per-function accessors.
>
> Suggested-by: Niklas Cassel <cassel@...nel.org>
> Signed-off-by: Aksh Garg <a-garg7@...com>
> Reviewed-by: Niklas Cassel <cassel@...nel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@....com>
>
> Changes from v4 to v5:
> - None
>
> Changes from v3 to v4:
> - Rebase
>
> Changes from v2 to v3:
> - Fixed the suggested nits
>
> v4: https://lore.kernel.org/all/20260129091753.490167-4-a-garg7@ti.com/
> v3: https://lore.kernel.org/all/20260127085010.446116-4-a-garg7@ti.com/
> v2: https://lore.kernel.org/all/20260122082538.309122-4-a-garg7@ti.com/
>
>  drivers/pci/controller/dwc/pcie-designware-ep.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 6d3c35dd280f..dd48e60b513c 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -1187,6 +1187,16 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
>  	if (ep->ops->init)
>  		ep->ops->init(ep);
>
> +	/*
> +	 * PCIe r6.0, section 7.9.15 states that for endpoints that support PTM,
> +	 * this capability structure is required in exactly one function, which
> +	 * controls the PTM behavior of all PTM capable functions. This indicates
> +	 * the PTM capability structure represents controller-level registers
> +	 * rather than per-function registers.
> +	 *
> +	 * Therefore, PTM capability registers are configured using the standard DBI
> +	 * accessors, instead of func_no indexed per-function accessors.
> +	 */
>  	ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
>
>  	/*
> --
> 2.34.1
>