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Message-ID: <aXzxLEiANRVVhBHP@tom-desktop>
Date: Fri, 30 Jan 2026 18:58:04 +0100
From: Tommaso Merciai <tommaso.merciai.xr@...renesas.com>
To: tomm.merciai@...il.com, geert@...ux-m68k.org,
laurent.pinchart@...asonboard.comy
Cc: linux-renesas-soc@...r.kernel.org, biju.das.jz@...renesas.com,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 00/20] Add support for DU and DSI on the Renesas
RZ/G3E SoC
On Fri, Jan 30, 2026 at 06:24:57PM +0100, Tommaso Merciai wrote:
> Dear All,
>
> This patch series adds support for the 2 Display Units (DUs) and MIPI DSI
> interface found on the Renesas RZ/G3E SoC.
>
> RZ/G3E SoC has 2 LCD controller (LCDC0 and LCDC1), both are composed
> of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD),
> and Display Unit (DU).
>
> LCDC0 is connected to LVDS (single or dual channel) and DSI.
> LCDC1 is connected to LVDS (single ch), DSI, and GPIO (Parallel I/F).
>
> Thanks & Regards,
> Tommaso
Please ignore this version I've made some mistake while
rebasing/squashing, sorry.
I will post v3.
Kind Regards,
Tommaso
>
> v1->v2:
> - Rebased on top of next-20260129.
> - PATCH 1: Added rzv2h_cpg_plldsi_smux_{get,set}_duty_cycle clock
> operations to allow the DRM driver to query and configure the
> appropriate clock path based on the required output duty cycle.
> Updated commit message accordingly.
> - PATCH 2-5: Collected tags.
> - PATCH 6: Moved clk_ids to match enum order.
> - PATCH 7: Collected GUytterhoeven tag. Fixed "dsi_0_vclk2" position
> to match order.
> - PATCH 8: Collected GUytterhoeven tag.
> - PATCH 9: Use single compatible string instead of multiple compatible
> strings for the two DU instances, leveraging a 'renesas,id' property
> to differentiate between DU0 and DU1. Updated commit message.
> - PATCH 10: Removed oneOf from clocks property, which is not sufficient
> to differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. Use the already
> existing vclk instead of vclk1 for RZ/G3E DSI bindings. Updated allOf.
> - PATCH 14: Instead of using clk-provider API to select the right parent
> clock, just set the correct duty cycle based on the output. Updated
> commit message accordingly.
> - PATCH 15-16: Collected tags.
> - PATCH 17: Squashed fcpvd0 and fcpvd1 patches into a single patch.
> Collected tags.
> - PATCH 18: Squashed vspd0 and vspd1 patches into a single patch.
> Collected tags.
> - PATCH 19: Reworked DU nodes to use single compatible. Use vclk instead
> of vclk1 for DSI Node and set to the right position.
> - PATCH 20: Fixed: dsi, du and adv7535 are part of the R9A09G047E57
> SMARC SoM board then add entries in the rzg3e-smarc-som.dtsi instead
> of using the r9a09g047e57-smarc-du1-adv7535.dtsi.
>
> Tommaso Merciai (20):
> clk: renesas: rzv2h: Add PLLDSI clk mux support
> clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support
> clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1} clocks
> clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_DIV7 clocks
> clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
> clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
> clk: renesas: r9a09g047: Add support for DSI clocks and resets
> clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
> dt-bindings: display: renesas,rzg2l-du: Add support for RZ/G3E SoC
> dt-bindings: display: bridge: renesas,dsi: Add support for RZ/G3E SoC
> drm: renesas: rz-du: mipi_dsi: Add out_port to OF data
> drm: renesas: rz-du: mipi_dsi: Add RZ_MIPI_DSI_FEATURE_GPO0R feature
> drm: renesas: rz-du: mipi_dsi: Add support for RZ/G3E
> drm: renesas: rz-du: Add RZ/G3E support
> media: dt-bindings: media: renesas,vsp1: Document RZ/G3E
> media: dt-bindings: media: renesas,fcp: Document RZ/G3E SoC
> arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes
> arm64: dts: renesas: r9a09g047: Add vspd{0,1} nodes
> arm64: dts: renesas: r9a09g047: Add DU{0,1} and DSI nodes
> arm64: dts: renesas: r9a09g047e57-smarc: Enable DU1 and DSI support
>
> .../bindings/display/bridge/renesas,dsi.yaml | 144 ++++++++++----
> .../bindings/display/renesas,rzg2l-du.yaml | 54 ++++++
> .../bindings/media/renesas,fcp.yaml | 2 +
> .../bindings/media/renesas,vsp1.yaml | 1 +
> arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 175 +++++++++++++++++
> .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 114 +++++++++++
> drivers/clk/renesas/r9a09g047-cpg.c | 84 +++++++++
> drivers/clk/renesas/rzv2h-cpg.c | 178 ++++++++++++++++++
> drivers/clk/renesas/rzv2h-cpg.h | 12 ++
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 48 +++++
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 26 +++
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 11 ++
> .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 105 ++++++++++-
> .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 3 +
> include/linux/clk/renesas.h | 20 ++
> 15 files changed, 933 insertions(+), 44 deletions(-)
>
> --
> 2.43.0
>
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