linux-kernel - Re: [PATCH v2 6/6] clk: qcom: Add TCSR clock driver for Eliza

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Message-ID: <2j3oraektgiphuj7akss3ytxgqt6e5kqt5gorkncjoiibol32e@aueznegzge2s>
Date: Fri, 30 Jan 2026 22:40:32 +0200
From: Abel Vesa <abel.vesa@....qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Luca Weiss <luca.weiss@...rphone.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Taniya Das <quic_tdas@...cinc.com>, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 6/6] clk: qcom: Add TCSR clock driver for Eliza

On 26-01-30 10:43:44, Konrad Dybcio wrote:
> On 1/28/26 3:10 PM, Abel Vesa wrote:
> > On 26-01-28 11:34:49, Konrad Dybcio wrote:
> >> On 1/27/26 4:03 PM, Abel Vesa wrote:
> >>> Add the TCSR clock controller that provides the refclks on Eliza
> >>> platform for PCIe, USB and UFS subsystems.
> >>>
> >>> Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> >>> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> >>> Signed-off-by: Abel Vesa <abel.vesa@....qualcomm.com>
> >>> ---
> >>
> >> [...]
> >>
> >>> +++ b/drivers/clk/qcom/tcsrcc-eliza.c
> >>> @@ -0,0 +1,144 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-only
> >>> +/*
> >>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> >>> + */
> >>> +
> >>> +#include <linux/clk-provider.h>
> >>> +#include <linux/mod_devicetable.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/platform_device.h>
> >>> +#include <linux/regmap.h>
> >>> +
> >>> +#include <dt-bindings/clock/qcom,eliza-tcsr.h>
> >>> +
> >>> +#include "clk-branch.h"
> >>> +#include "clk-regmap.h"
> >>> +#include "common.h"
> >>> +
> >>> +enum {
> >>> +	DT_BI_TCXO_PAD,
> >>> +};
> >>> +
> >>> +static struct clk_branch tcsr_pcie_0_clkref_en = {
> >>> +	.halt_reg = 0x0,
> >>
> >> These regs certainly aren't at +0x0 to what we normally expect to
> >> be the start of the TCSR node
> > 
> > They are if we add the TCSR node with reg range starting at 0x1fbf000.
> 
> "if we take the wrong base, the wrong offset is right" ;)
> 
> The docs for Eliza don't have the nice separation like on e.g. Hamoa,
> but 0x01fc0000 is what we generally agreed upon to be "tcsr".
> 
> The registers that first appear in that region are the same as on Hamoa,
> and so is the address, so let's continue that tradition

Sure.