linux-kernel - Re: [PATCH v6 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <64x5xfzjik4qtvsxqvwqhf5mua3rpvh7nzw67v5sy7afoo5fzv@5vp3uvjk66if>
Date: Sat, 31 Jan 2026 00:00:34 +0200
From: Abel Vesa <abel.vesa@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>,
        Maulik Shah <maulik.shah@....qualcomm.com>,
        Sibi Sankar <sibi.sankar@....qualcomm.com>,
        Taniya Das <taniya.das@....qualcomm.com>,
        Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>,
        Qiang Yu <qiang.yu@....qualcomm.com>,
        Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>,
        Jishnu Prakash <jishnu.prakash@....qualcomm.com>,
        Abel Vesa <abelvesa@...nel.org>
Subject: Re: [PATCH v6 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

On 26-01-30 23:44:43, Abel Vesa wrote:
> On 26-01-22 20:54:00, Pankaj Patil wrote:
> > Introduce the base device tree support for Glymur – Qualcomm's
> > next-generation compute SoC. The new glymur.dtsi describes the core SoC
> > components, including:
> > 
> > - CPUs and CPU topology
> > - Interrupt controller and TLMM
> > - GCC,DISPCC and RPMHCC clock controllers
> > - Reserved memory and interconnects
> > - APPS and PCIe SMMU and firmware SCM
> > - Watchdog, RPMHPD, APPS RSC and SRAM
> > - PSCI and PMU nodes
> > - QUPv3 serial engines
> > - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
> > - PDP0 mailbox, IPCC and AOSS
> > - Display clock controller
> > - SPMI PMIC arbiter with SPMI0/1/2 buses
> > - SMP2P nodes
> > - TSENS and thermal zones (8 instances, 92 sensors)
> > 
> > Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
> > PMH0110, PMIC's along with temp-alarm and GPIO nodes needed on Glymur
> > 
> > Enabled PCIe controllers and associated PHY to support boot to
> > shell with nvme storage,
> > List of PCIe instances enabled:
> > 
> > - PCIe3b
> > - PCIe4
> > - PCIe5
> > - PCIe6
> > 
> > Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@....qualcomm.com>
> > Co-developed-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > Signed-off-by: Maulik Shah <maulik.shah@....qualcomm.com>
> > Co-developed-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > Signed-off-by: Sibi Sankar <sibi.sankar@....qualcomm.com>
> > Co-developed-by: Taniya Das <taniya.das@....qualcomm.com>
> > Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> > Co-developed-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > Signed-off-by: Kamal Wadhwa <kamal.wadhwa@....qualcomm.com>
> > Co-developed-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> > Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
> > Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
> > Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@....qualcomm.com>
> > Co-developed-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > Signed-off-by: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> > ---
> >  arch/arm64/boot/dts/qcom/glymur.dtsi         | 5913 ++++++++++++++++++++++++++
> >  arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  187 +
> >  arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   68 +
> >  arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |  144 +
> >  arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |  144 +
> >  arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
> >  arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
> >  7 files changed, 6571 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > new file mode 100644
> > index 000000000000..16a3c3ecf97a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> 
> [...]
> 
> > +
> > +	soc: soc@0 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
> > +		dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
> > +
> > +		gcc: clock-controller@...000 {
> > +			compatible = "qcom,glymur-gcc";
> > +			reg = <0x0 0x00100000 0x0 0x1f9000>;
> > +			clocks = <&rpmhcc RPMH_CXO_CLK>,
> > +				 <&rpmhcc RPMH_CXO_CLK_A>,
> > +				 <&sleep_clk>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <0>,
> > +				 <&pcie3b_phy>,
> > +				 <&pcie4_phy>,
> > +				 <&pcie5_phy>,
> > +				 <&pcie6_phy>,
> 
> I'm afraid these do not match the array from the driver.
> I think there is one more <0> before the pcie3b.

Actually, one less.

> 
> Please double check.
> 
> Thanks,
> Abel