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Message-ID: <df8d5d5f28870752e77ec74f34fea7ceb6e97286.camel@ndufresne.ca>
Date: Fri, 30 Jan 2026 09:47:34 -0500
From: Nicolas Dufresne <nicolas@...fresne.ca>
To: ming.qian@....nxp.com, linux-media@...r.kernel.org
Cc: mchehab@...nel.org, hverkuil-cisco@...all.nl,
benjamin.gaignard@...labora.com, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, p.zabel@...gutronix.de,
sebastian.fricke@...labora.com, shawnguo@...nel.org,
ulf.hansson@...aro.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
festevam@...il.com, linux-imx@....com, l.stach@...gutronix.de,
Frank.li@....com, peng.fan@....com, eagle.zhou@....com,
devicetree@...r.kernel.org, imx@...ts.linux.dev, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH] arm64: dts: imx8mq: Restore VPU G2 clock to 600MHz for
4K60fps decoding
Hi,
Le vendredi 30 janvier 2026 à 16:41 +0800, ming.qian@....nxp.com a écrit :
> From: Ming Qian <ming.qian@....nxp.com>
>
> The VPU G2 clock was reduced from 600MHz to 300MHz in commit
> b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock") to address
> pixel errors with high-resolution HEVC postprocessor output.
>
> However, testing shows the 300MHz clock rate is insufficient for
> 4K60fps decoding and the original pixel errors no longer occur at
> 600MHz with current drivers.
Tested on EVK, with the downstream DCSS driver, and this change triggers DCSS
underrun (which is related to the DRAM QoS erratas on this SoC). It also
sometimes trigger the "not all macroblock decoded" warning I added recently, and
we can empty IRQs, but these are handled now.
>
> Test results with 3840x2160@...ps HEVC stream decoded to NV12
> (the same scenario that exhibited pixel errors previously):
>
> 300MHz performance:
> - Severe frame dropping throughout playback
> - Only 336 frames rendered in 11:53 (0.471 fps)
> - Continuous "A lot of buffers are being dropped" warnings
> - Completely unusable for 4K video
>
> 600MHz performance:
> - Smooth playback with only 1 frame dropped at startup
> - 37981 frames rendered in 10:34 (59.857 fps)
> - Achieves target 60fps performance
> - No pixel errors or artifacts observed
That probably only true with the upstream DCSS + a small resolution embedded
panel ? Can you clarify this setup, because the display drivers mainline are
very minimal. Would be nice to show you average DDR read/write bandwidth
utilization during this run for comparision.
Another information that bugs me, in the BSP code, the G2 voltage is increased
too, which you didn't do here. They also use the thermal 2 zone to kick it down
to 300 until it cools down.
Nicolas
>
> Restore the clock to 600MHz to enable proper 4K60fps decoding
> capability while maintaining stability.
>
> Test pipeline:
> gst-launch-1.0 filesrc location=<4K60_HEVC.mkv> ! \
> video/x-matroska ! aiurdemux ! h265parse ! \
> v4l2slh265dec ! video/x-raw,format=NV12 ! \
> queue ! waylandsink
>
> Fixes: b27bfc5103c7 ("arm64: dts: freescale: Fix VPU G2 clock")
> Signed-off-by: Ming Qian <ming.qian@....nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 607962f807be..731142176625 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -960,7 +960,7 @@ pgc_vpu: power-domain@6 {
>
> <&clk IMX8MQ_SYS1_PLL_800M>,
>
> <&clk IMX8MQ_VPU_PLL>;
> assigned-clock-rates =
> <600000000>,
> -
> <300000000>,
> +
> <600000000>,
>
> <800000000>,
> <0>;
> };
>
> base-commit: c824345288d11e269ce41b36c105715bc2286050
> prerequisite-patch-id: 0000000000000000000000000000000000000000
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