linux-kernel - Re: [v4,2/4] net: phy: realtek: add RTL8224 pair order support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20260131015320.971482-1-kuba@kernel.org>
Date: Fri, 30 Jan 2026 17:53:20 -0800
From: Jakub Kicinski <kuba@...nel.org>
To: dam.dejean@...il.com
Cc: Jakub Kicinski <kuba@...nel.org>,
	robh@...nel.org,
	krzk+dt@...nel.org,
	andrew@...n.ch,
	davem@...emloft.net,
	hkallweit1@...il.com,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	pabeni@...hat.com,
	netdev@...r.kernel.org,
	edumazet@...gle.com
Subject: Re: [v4,2/4] net: phy: realtek: add RTL8224 pair order support

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.

For local reproduction steps see https://netdev-ai.bots.linux.dev/ai-local.html
---
net: phy: realtek: add RTL8224 pair order support

This patch adds MDI pair order configuration support for the RTL8224 PHY,
allowing device tree configuration of pair swap (ABCD to DCBA) via the
enet-phy-lane-order property.

> diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c
> --- a/drivers/net/phy/realtek/realtek_main.c
> +++ b/drivers/net/phy/realtek/realtek_main.c

[ ... ]

> +static int rtl8224_mdi_config_order(struct phy_device *phydev)
> +{
> +	struct device_node *np = phydev->mdio.dev.of_node;
> +	u8 port_offset = phydev->mdio.addr & 3;
> +	u32 order = 0;
> +	int ret, val;
> +
> +	ret = of_property_read_u32(np, "enet-phy-lane-order", &order);
> +
> +	/* Do nothing in case the property is not present */
> +	if (ret == -EINVAL)
> +		return 0;
> +
> +	if (ret)
> +		return ret;
> +
> +	if (order & ~1)
> +		return -EINVAL;
> +
> +	val = __phy_package_read_mmd(phydev, 0, MDIO_MMD_VEND1,
> +				     RTL8224_VND1_MDI_PAIR_SWAP);

Should the MDIO bus lock be held before calling __phy_package_read_mmd()?

The __phy_package_read_mmd() documentation states "Same calling rules as
for __phy_read()", and __phy_read() requires: "The caller must have taken
the MDIO bus lock."

Looking at __mdiobus_read(), there is a lockdep_assert_held_once() check
for bus->mdio_lock, which confirms this requirement.

Other PHY drivers using these APIs acquire the lock first. For example,
qca807x_phy_package_config_init_once() wraps its __phy_package_read_mmd()
calls with phy_lock_mdio_bus()/phy_unlock_mdio_bus().

Additionally, since this is a read-modify-write on a shared register that
contains bits for all 4 ports in the package, could concurrent config_init
calls from different ports race and overwrite each other's settings without
the lock protecting the entire sequence?

> +	if (val < 0)
> +		return val;
> +
> +	if (order)
> +		val |= (1 << port_offset);
> +	else
> +		val &= ~(1 << port_offset);
> +
> +	return __phy_package_write_mmd(phydev, 0, MDIO_MMD_VEND1,
> +				       RTL8224_VND1_MDI_PAIR_SWAP, val);
> +}
-- 
pw-bot: cr