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Message-ID:
<OS7PR01MB13602AEB5907C4B1B85767DA8BC9CA@OS7PR01MB13602.jpnprd01.prod.outlook.com>
Date: Sat, 31 Jan 2026 13:27:29 +0800
From: Shiji Yang <yangshiji66@...look.com>
To: linux-mtd@...ts.infradead.org
Cc: Tudor Ambarus <tudor.ambarus@...aro.org>,
Pratyush Yadav <pratyush@...nel.org>,
Michael Walle <mwalle@...nel.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
Nick Hainke <vincent@...temli.org>,
linux-kernel@...r.kernel.org,
Shiji Yang <yangshiji66@...look.com>
Subject: [PATCH] mtd: spi-nor: macronix: locking support for MX25L6405D
Macronix MX25L6405D supports locking with four block-protection bits.
The old revision chips only have status register 1. Hence we also have
to clear the 16BIT_SR flag so that the SR1 can be updated correctly.
Co-authored-by: Nick Hainke <vincent@...temli.org>
Signed-off-by: Shiji Yang <yangshiji66@...look.com>
---
drivers/mtd/spi-nor/macronix.c | 11 +++++++++++
1 file changed, 11 insertions(+)
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -8,6 +8,11 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+static void macronix_no_16bit_sr_default_init(struct spi_nor *nor)
+{
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+}
+
static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
@@ -28,6 +33,10 @@ mx25l25635_post_bfpt_fixups(struct spi_n
return 0;
}
+static const struct spi_nor_fixups mx25l64_fixups = {
+ .default_init = macronix_no_16bit_sr_default_init,
+};
+
static const struct spi_nor_fixups mx25l25635_fixups = {
.post_bfpt = mx25l25635_post_bfpt_fixups,
.post_sfdp = macronix_qpp4b_post_sfdp_fixups,
@@ -66,7 +75,9 @@ static const struct flash_info macronix_
.id = SNOR_ID(0xc2, 0x20, 0x17),
.name = "mx25l6405d",
.size = SZ_8M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
.no_sfdp_flags = SECT_4K,
+ .fixups = &mx25l64_fixups,
}, {
/* MX25L12805D */
.id = SNOR_ID(0xc2, 0x20, 0x18),
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