linux-kernel - Re: [PATCH net-next] net: stmmac: dwmac-loongson: Set clk_csr

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4d1abb0c-e518-4751-b462-345ed76bb3f1@lunn.ch>
Date: Mon, 2 Feb 2026 22:42:14 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Huacai Chen <chenhuacai@...ngson.cn>
Cc: Huacai Chen <chenhuacai@...nel.org>,
	Andrew Lunn <andrew+netdev@...n.ch>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Yanteng Si <si.yanteng@...ux.dev>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Jose Abreu <joabreu@...opsys.com>,
	Serge Semin <fancer.lancer@...il.com>, loongarch@...ts.linux.dev,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	stable@...r.kernel.org, Hongliang Wang <wanghongliang@...ngson.cn>
Subject: Re: [PATCH net-next] net: stmmac: dwmac-loongson: Set clk_csr_i to
 100-150MHz

On Sun, Feb 01, 2026 at 10:37:00AM +0800, Huacai Chen wrote:
> Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
> and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
> Loongson STMMAC use 125MHz clocks and need 62 freq division to within
> 2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
> to 100-150MHz.
> 
> Cc: stable@...r.kernel.org
> Signed-off-by: Hongliang Wang <wanghongliang@...ngson.cn>
> Signed-off-by: Huacai Chen <chenhuacai@...ngson.cn>

Fixes tag?

Does the error mean that MDC is ticking at 9.7Mhz? That is pretty fast
for PHYs. But i assume it must work for some boards.

Separate to this fix, you might be interested in:

  clock-frequency:
    description:
      Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
      defined 2.5MHz should only be used when all devices on the bus support
      the given clock speed.

So you could allow faster MDC values using this property.

    Andrew

---
pw-bot: cr