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Message-ID: <20260203-upstream_uboot_properties-v6-5-0a2280e84d31@foss.st.com>
Date: Tue, 3 Feb 2026 15:28:11 +0100
From: Patrice Chotard <patrice.chotard@...s.st.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Maxime Coquelin
<mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...s.st.com>,
Patrick Delaunay <patrick.delaunay@...s.st.com>, Christoph Niedermaier
<cniedermaier@...electronics.com>, Marek Vasut <marex@...x.de>
CC: <devicetree@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<kernel@...electronics.com>, Patrice Chotard <patrice.chotard@...s.st.com>
Subject: [PATCH v6 5/7] ARM: dts: stm32: Add boot phase tags for
STMicroelectronics mp13 boards
The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.
Signed-off-by: Patrice Chotard <patrice.chotard@...s.st.com>
---
arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +-
arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 +++++
arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 +++++++++++++++++++++++
arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 101 +++++++++++++++++++++++
4 files changed, 225 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index b9657ff91c23..3d77bdaa945a 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -36,7 +36,7 @@ arm_wdt: watchdog {
};
firmware {
- optee {
+ optee: optee {
method = "smc";
compatible = "linaro,optee-tz";
interrupt-parent = <&intc>;
@@ -91,7 +91,7 @@ intc: interrupt-controller@...21000 {
<0xa0022000 0x2000>;
};
- psci {
+ psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
index 9902849ed040..526ab2e1a93c 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
@@ -350,6 +350,21 @@ timer@12 {
};
};
+&uart4 {
+ bootph-all;
+};
+
+&uart4_pins_b {
+ bootph-all;
+
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart1_pins_b>;
@@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
status = "okay";
};
+&usbphyc {
+ bootph-all;
+};
+
&usbh_ehci {
phys = <&usbphyc_port0>;
status = "okay";
@@ -432,6 +451,7 @@ connector {
/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
&vdd_ldo2 {
+ bootph-all;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
@@ -440,6 +460,7 @@ &vdd_ldo2 {
/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
&vdd_sd {
+ bootph-all;
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 8dcf68b212b4..59c0d41acd54 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -179,6 +179,10 @@ &arm_wdt {
status = "okay";
};
+&bsec {
+ bootph-all;
+};
+
&crc1 {
status = "okay";
};
@@ -226,6 +230,42 @@ phy0_eth1: ethernet-phy@0 {
};
};
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
&i2c1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_a>;
@@ -360,6 +400,7 @@ goodix: goodix-ts@5d {
&iwdg2 {
timeout-sec = <32>;
+ bootph-all;
status = "okay";
};
@@ -367,6 +408,7 @@ <dc {
pinctrl-names = "default", "sleep";
pinctrl-0 = <<dc_pins_a>;
pinctrl-1 = <<dc_sleep_pins_a>;
+ bootph-some-ram;
status = "okay";
port {
@@ -376,6 +418,22 @@ ltdc_out_rgb: endpoint {
};
};
+&optee {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&psci {
+ bootph-some-ram;
+};
+
+&rcc {
+ bootph-all;
+};
+
&rtc {
pinctrl-names = "default";
pinctrl-0 = <&rtc_rsvd_pins_a>;
@@ -387,6 +445,14 @@ rtc_lsco_pins_a: rtc-lsco-0 {
};
};
+&scmi {
+ bootph-all;
+};
+
+&scmi_clk {
+ bootph-all;
+};
+
&scmi_regu {
scmi_vdd_adc: regulator@10 {
reg = <VOLTD_SCMI_STPMIC1_LDO1>;
@@ -410,6 +476,10 @@ scmi_v3v3_sw: regulator@19 {
};
};
+&scmi_reset {
+ bootph-all;
+};
+
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
@@ -420,9 +490,24 @@ &sdmmc1 {
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&scmi_vdd_sd>;
+ bootph-pre-ram;
status = "okay";
};
+&sdmmc1_b4_pins_a {
+ bootph-pre-ram;
+ pins {
+ bootph-pre-ram;
+ };
+};
+
+&sdmmc1_clk_pins_a {
+ bootph-pre-ram;
+ pins {
+ bootph-pre-ram;
+ };
+};
+
/* Wifi */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
@@ -454,6 +539,10 @@ &spi5 {
status = "disabled";
};
+&syscfg {
+ bootph-all;
+};
+
&timers3 {
/delete-property/dmas;
/delete-property/dma-names;
@@ -535,9 +624,20 @@ &uart4 {
pinctrl-2 = <&uart4_idle_pins_a>;
/delete-property/dmas;
/delete-property/dma-names;
+ bootph-all;
status = "okay";
};
+&uart4_pins_a {
+ bootph-all;
+ pins1 {
+ bootph-all;
+ };
+ pins2 {
+ bootph-all;
+ };
+};
+
&uart8 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&uart8_pins_a>;
@@ -601,6 +701,7 @@ usbotg_hs_ep: endpoint {
};
&usbphyc {
+ bootph-all;
status = "okay";
};
diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
index 54ece71085c1..4efaca84a72c 100644
--- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
@@ -54,6 +54,46 @@ vin: vin {
};
};
+&bsec {
+ bootph-all;
+};
+
+&gpioa {
+ bootph-all;
+};
+
+&gpiob {
+ bootph-all;
+};
+
+&gpioc {
+ bootph-all;
+};
+
+&gpiod {
+ bootph-all;
+};
+
+&gpioe {
+ bootph-all;
+};
+
+&gpiof {
+ bootph-all;
+};
+
+&gpiog {
+ bootph-all;
+};
+
+&gpioh {
+ bootph-all;
+};
+
+&gpioi {
+ bootph-all;
+};
+
&i2c3 {
i2c-scl-rising-time-ns = <96>;
i2c-scl-falling-time-ns = <3>;
@@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 {
&iwdg2 {
timeout-sec = <32>;
+ bootph-all;
status = "okay";
};
+&pinctrl {
+ bootph-all;
+};
+
+&psci {
+ bootph-some-ram;
+};
+
&qspi {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qspi_clk_pins_a
@@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a
&qspi_cs1_sleep_pins_a>;
#address-cells = <1>;
#size-cells = <0>;
+ bootph-all;
status = "okay";
flash0: flash@0 {
@@ -238,9 +288,35 @@ flash0: flash@0 {
spi-max-frequency = <108000000>;
#address-cells = <1>;
#size-cells = <1>;
+ bootph-all;
};
};
+&qspi_clk_pins_a {
+ bootph-all;
+ pins {
+ bootph-all;
+ };
+};
+
+&qspi_bk1_pins_a {
+ bootph-all;
+ pins {
+ bootph-all;
+ };
+};
+
+&qspi_cs1_pins_a {
+ bootph-all;
+ pins {
+ bootph-all;
+ };
+};
+
+&rcc {
+ bootph-all;
+};
+
/* SDIO WiFi */
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
@@ -285,6 +361,10 @@ &sdmmc2 {
status = "okay";
};
+&syscfg {
+ bootph-all;
+};
+
/* Console UART */
&uart4 {
pinctrl-names = "default", "sleep", "idle";
@@ -312,3 +392,24 @@ bluetooth {
shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
};
};
+
+&vdd {
+ bootph-all;
+};
+
+&vddcpu {
+ bootph-all;
+};
+
+
+&vddcore {
+ bootph-all;
+};
+
+&vdd_ddr {
+ bootph-all;
+};
+
+&vref_ddr {
+ bootph-all;
+};
--
2.43.0
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