linux-kernel - [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache

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Message-ID: <20260203161843.649417-1-wangyushan12@huawei.com>
Date: Wed, 4 Feb 2026 00:18:40 +0800
From: Yushan Wang <wangyushan12@...wei.com>
To: <alexandre.belloni@...tlin.com>, <arnd@...db.de>, <fustini@...nel.org>,
	<Jonathan.Cameron@...wei.com>, <krzk@...nel.org>, <linus.walleij@...aro.org>,
	<will@...nel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-kernel@...r.kernel.org>
CC: <fanghao11@...wei.com>, <linuxarm@...wei.com>, <liuyonglong@...wei.com>,
	<prime.zeng@...ilicon.com>, <wangzhou1@...ilicon.com>,
	<xuwei5@...ilicon.com>, <wangyushan12@...wei.com>
Subject: [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache

Provide support for L3 cache lockdown on HiSilicon L3 caches.

Cache lockdown means to make a memory region locked inside the L3 cache
for better access latency. The data stored in L3 cache will behave like
any other data (i.e. it still follows cache coherency protocol etc.)
except it won't be evicted unless explicitly asked to by deallocation.
This way a process may have an option to maintain QoS even with noisy
neighbors sharing the same L3 cache.

Ideally locked data will have stable low access latency despite high
background stress. It is also useful for scenarios that have especially
high cache miss penalty. However, while enhancing some processes,
reserving cache resource will raise the performance problem to other
processes running on the CPUs that share the L3 cache that carries
locked data, users should be careful to do so.

---

Changes since RFC v2:
- Fixed compile errors for x86 building.
- Link to v2: https://lore.kernel.org/all/20251217102357.1730573-1-wangyushan12@huawei.com/

Changes since RFC v1:
- Fixed compile errors of types specified in uapi header files.
- Changed ioctl numbers to avoid confliction.
- Link to v1: https://lore.kernel.org/all/20251125080542.3721829-1-wangyushan12@huawei.com/

Yushan Wang (3):
  soc cache: L3 cache driver for HiSilicon SoC
  soc cache: L3 cache lockdown support for HiSilicon SoC
  Documentation: soc cache: Add documentation to HiSilicon SoC cache

 Documentation/driver-api/hisi-soc-cache.rst   |  64 ++
 Documentation/driver-api/index.rst            |   1 +
 .../userspace-api/ioctl/ioctl-number.rst      |   1 +
 MAINTAINERS                                   |   7 +
 drivers/soc/hisilicon/Kconfig                 |  11 +
 drivers/soc/hisilicon/Makefile                |   2 +
 drivers/soc/hisilicon/hisi_soc_l3c.c          | 883 ++++++++++++++++++
 include/uapi/misc/hisi_l3c.h                  |  28 +
 8 files changed, 997 insertions(+)
 create mode 100644 Documentation/driver-api/hisi-soc-cache.rst
 create mode 100644 drivers/soc/hisilicon/hisi_soc_l3c.c
 create mode 100644 include/uapi/misc/hisi_l3c.h

-- 
2.33.0