linux-kernel - [PATCH v3 2/2] dt-binding: riscv: Clarify the riscv,ndev meaning in PLIC

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Message-ID: <tencent_720A4669773B1EE15EC720869C35C2F0490A@qq.com>
Date: Wed,  4 Feb 2026 01:21:48 +0800
From: Yangyu Chen <cyy@...self.name>
To: linux-riscv@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org,
	Anup Patel <anup.patel@....qualcomm.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Charles Mirabile <cmirabil@...hat.com>,
	Lucas Zampieri <lzampier@...hat.com>,
	Thomas Gleixner <tglx@...nel.org>,
	Paul Walmsley <pjw@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Mason Huo <mason.huo@...rfivetech.com>,
	Zhang Xincheng <zhangxincheng@...rarisc.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Marc Zyngier <maz@...nel.org>,
	Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
	Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Alexandre Ghiti <alex@...ti.fr>,
	devicetree@...r.kernel.org,
	Jia Wang <wangjia@...rarisc.com>,
	Yangyu Chen <cyy@...self.name>
Subject: [PATCH v3 2/2] dt-binding: riscv: Clarify the riscv,ndev meaning in PLIC

In PLIC, interrupt source 0 is reserved and should not be used.
Therefore, the valid interrupt sources are from 1 to riscv,ndev
inclusive. This commit updates the documentation to clarify this point.

Signed-off-by: Yangyu Chen <cyy@...self.name>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 388fc2c620c0..df9578bcac89 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -109,6 +109,8 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       Specifies how many external interrupts are supported by this controller.
+      Note that source 0 is reserved in PLIC, so the valid interrupt sources
+      are 1 to riscv,ndev inclusive.
 
   clocks: true
 
-- 
2.51.0