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Message-ID: <75c590f9-aa08-4b8d-8dbf-422273012c74@bootlin.com>
Date: Tue, 3 Feb 2026 10:09:49 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: Damien Dejean <dam.dejean@...il.com>, andrew@...n.ch, krzk+dt@...nel.org,
robh@...nel.org, kuba@...nel.org
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, edumazet@...gle.com, davem@...emloft.net,
pabeni@...hat.com, hkallweit1@...il.com
Subject: Re: [PATCH v5 1/4] dt-bindings: net: ethernet-phy: add property
enet-phy-lane-order
Hi,
On 02/02/2026 21:04, Damien Dejean wrote:
> Add property enet-phy-lane-order to the device tree bindings to define
> the lane order of the PHY. To simplify PCB design some manufacturers
> allow to wire the pairs in a reverse order, and change the order in
> software.
>
> The property can be set to 0 to force the normal lane order (ABCD), or 1
> to force the reverse lane order (DCBA).
>
> Signed-off-by: Damien Dejean <dam.dejean@...il.com>
> ---
> Documentation/devicetree/bindings/net/ethernet-phy.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
> index 58634fee9fc4..8347d4e134d2 100644
> --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml
> +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml
> @@ -126,6 +126,12 @@ properties:
> e.g. wrong bootstrap configuration caused by issues in PCB
> layout design.
>
> + enet-phy-lane-order:
As this is specific to BaseT, maybe rename that "enet-phy-pair-order" ?
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [0, 1]
> + description:
> + For normal (0) or reverse (1) order of the pairs (ABCD -> DCBA).
We now have a binding in DT for ethernet-connectors, and I'd says this
is typically the kind of info I'd put in there :
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/tree/Documentation/devicetree/bindings/net/ethernet-connector.yaml
The way you'd use that is by adding a ".attach_mdi_port()" callback in your
phy driver, and in there you'd parse these properties and do the proper settings.
We're missing a few things, such as storing a ref to the of_node corresponding
to the connector into phy_port.
This is brand new though, maybe Maintainers would like for phy_port to stabilize
before building more on top of it ?
Maxime
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