linux-kernel - Re: [PATCH 1/2] x86/ioapic: Add NMI delivery configuration helper

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <d2309f78aa999c65a29172011e6122109d553ffd.camel@infradead.org>
Date: Tue, 03 Feb 2026 10:45:02 +0000
From: David Woodhouse <dwmw2@...radead.org>
To: Thomas Gleixner <tglx@...nel.org>, Alexander Graf <graf@...zon.com>, 
	x86@...nel.org
Cc: linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, Clemens Ladisch
 <clemens@...isch.de>, Arnd Bergmann <arnd@...db.de>, Greg Kroah-Hartman
 <gregkh@...uxfoundation.org>, Dave Hansen <dave.hansen@...ux.intel.com>, 
 Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>, Jonathan
 Corbet <corbet@....net>,  Paolo Bonzini <pbonzini@...hat.com>, Pasha
 Tatashin <pasha.tatashin@...een.com>, nh-open-source@...zon.com,  Nicolas
 Saenz Julienne <nsaenz@...zon.es>, Hendrik Borghorst <hborghor@...zon.de>,
 Filippo Sironi <sironi@...zon.de>, Jan Schönherr
 <jschoenh@...zon.de>
Subject: Re: [PATCH 1/2] x86/ioapic: Add NMI delivery configuration helper

On Tue, 2026-02-03 at 11:08 +0100, Thomas Gleixner wrote:
> On Mon, Feb 02 2026 at 17:48, Alexander Graf wrote:
> > To implement an HPET based NMI watchdog, the HPET code will need to
> > reconfigure an IOAPIC pin to NMI mode. Add a function that allows driver
> > code to configure an IOAPIC pin for NMI delivery mode.
> 
> A function which violates all layering of the interrupt hierarchy...

I think you mean that this should be done by composing an MSI message
accordingly, and letting ioapic_setup_msg_from_msi() convert that into
an RTE for the I/O APIC without messing with the content? None of this
part should be specific to the I/O APIC?

And of course, if you're generating the MSI message you could just have
the HPET raise that directly instead of using a line interrupt, right?

> > +/**
> > + * ioapic_set_nmi - Configure an IOAPIC pin for NMI delivery
> > + * @gsi: Global System Interrupt number
> > + * @broadcast: true to broadcast to all CPUs, false to send to CPU 0 only
> > + *
> > + * Configures the specified GSI for NMI delivery mode.
> > + *
> > + * Returns 0 on success, negative error code on failure.
> > + */
> > +int ioapic_set_nmi(u32 gsi, bool broadcast)
> > +{
> > +	struct IO_APIC_route_entry entry = { };
> > +	int ioapic_idx, pin;
> > +
> > +	ioapic_idx = mp_find_ioapic(gsi);
> > +	if (ioapic_idx < 0)
> > +		return -ENODEV;
> > +
> > +	pin = mp_find_ioapic_pin(ioapic_idx, gsi);
> > +	if (pin < 0)
> > +		return -ENODEV;
> > +
> > +	entry.delivery_mode = APIC_DELIVERY_MODE_NMI;
> > +	entry.destid_0_7 = broadcast ? 0xFF : boot_cpu_physical_apicid;

How does that work in x2apic mode? Broadcast isn't 0xff there, is it?
And for systems with 15-bit MSI support you would also want to fill in
the extra 7 bits? But the MSI message composition function should
handle that for you anyway, right?


Download attachment "smime.p7s" of type "application/pkcs7-signature" (5069 bytes)