lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20260204142320.103184-2-biju.das.jz@bp.renesas.com>
Date: Wed,  4 Feb 2026 14:23:09 +0000
From: Biju <biju.das.au@...il.com>
To: Thomas Gleixner <tglx@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>
Cc: Biju Das <biju.das.jz@...renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	Biju Das <biju.das.au@...il.com>
Subject: [PATCH 1/8] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC

From: Biju Das <biju.das.jz@...renesas.com>

Document RZ/G3L (R9A08G046) IRQC bindings. The IRQC block on RZ/G3L SoC
is almost identical to one found on the RZ/G3S SoC with the difference
like it support more External IRQs, GPT Error Interrupts and also has
additional registers for GPT/MTU IRQ selection, shared IRQ selection
between external IRQ and TINT. Hence new generic compatible string
"renesas,r9a08g046-irqc" is added for RZ/G3L SoC.

Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
 .../renesas,rzg2l-irqc.yaml                   | 66 +++++++++++++++++--
 1 file changed, 62 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 44b6ae5fc802..6ee81663f0a1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -30,7 +30,10 @@ properties:
               - renesas,r9a08g045-irqc     # RZ/G3S
           - const: renesas,rzg2l-irqc
 
-      - const: renesas,r9a07g043f-irqc     # RZ/Five
+      - items:
+          - enum:
+              - renesas,r9a07g043f-irqc    # RZ/Five
+              - renesas,r9a08g046-irqc     # RZ/G3L
 
   '#interrupt-cells':
     description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
@@ -58,6 +61,14 @@ properties:
       - description: IRQ5 interrupt
       - description: IRQ6 interrupt
       - description: IRQ7 interrupt
+      - description: IRQ8 interrupt
+      - description: IRQ9 interrupt
+      - description: IRQ10 interrupt
+      - description: IRQ11 interrupt
+      - description: IRQ12 interrupt
+      - description: IRQ13 interrupt
+      - description: IRQ14 interrupt
+      - description: IRQ15 interrupt
       - description: GPIO interrupt, TINT0
       - description: GPIO interrupt, TINT1
       - description: GPIO interrupt, TINT2
@@ -97,6 +108,14 @@ properties:
       - description: ECCRAM1 1bit error interrupt
       - description: ECCRAM1 2bit error interrupt
       - description: ECCRAM1 error overflow interrupt
+      - description: Integrated GPT Error interrupt for channel 0, OVFUNF0
+      - description: Integrated GPT Error interrupt for channel 1, OVFUNF1
+      - description: Integrated GPT Error interrupt for channel 2, OVFUNF2
+      - description: Integrated GPT Error interrupt for channel 3, OVFUNF3
+      - description: Integrated GPT Error interrupt for channel 4, OVFUNF4
+      - description: Integrated GPT Error interrupt for channel 5, OVFUNF5
+      - description: Integrated GPT Error interrupt for channel 6, OVFUNF6
+      - description: Integrated GPT Error interrupt for channel 7, OVFUNF7
 
   interrupt-names:
     minItems: 45
@@ -110,6 +129,14 @@ properties:
       - const: irq5
       - const: irq6
       - const: irq7
+      - const: irq8
+      - const: irq9
+      - const: irq10
+      - const: irq11
+      - const: irq12
+      - const: irq13
+      - const: irq14
+      - const: irq15
       - const: tint0
       - const: tint1
       - const: tint2
@@ -149,6 +176,14 @@ properties:
       - const: ec7tie1-1
       - const: ec7tie2-1
       - const: ec7tiovf-1
+      - const: ovfunf0
+      - const: ovfunf1
+      - const: ovfunf2
+      - const: ovfunf3
+      - const: ovfunf4
+      - const: ovfunf5
+      - const: ovfunf6
+      - const: ovfunf7
 
   clocks:
     maxItems: 2
@@ -180,6 +215,22 @@ required:
 allOf:
   - $ref: /schemas/interrupt-controller.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g043f-irqc
+              - renesas,r9a07g043u-irqc
+              - renesas,r9a07g044-irqc
+              - renesas,r9a07g054-irqc
+    then:
+      properties:
+        interrupts:
+          maxItems: 48
+        interrupt-names:
+          maxItems: 48
+
   - if:
       properties:
         compatible:
@@ -192,12 +243,19 @@ allOf:
           maxItems: 45
         interrupt-names:
           maxItems: 45
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a08g046-irqc
+    then:
       properties:
         interrupts:
-          minItems: 48
+          maxItems: 61
         interrupt-names:
-          minItems: 48
+          maxItems: 61
 
 unevaluatedProperties: false
 
-- 
2.43.0


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ