linux-kernel - Re: [PATCH v3 2/2] dt-binding: riscv: Clarify the riscv,ndev meaning in PLIC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20260204-cursor-wad-186f59d9c2ab@spud>
Date: Wed, 4 Feb 2026 17:49:47 +0000
From: Conor Dooley <conor@...nel.org>
To: Yangyu Chen <cyy@...self.name>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Anup Patel <anup.patel@....qualcomm.com>,
	Samuel Holland <samuel.holland@...ive.com>,
	Charles Mirabile <cmirabil@...hat.com>,
	Lucas Zampieri <lzampier@...hat.com>,
	Thomas Gleixner <tglx@...nel.org>, Paul Walmsley <pjw@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Mason Huo <mason.huo@...rfivetech.com>,
	Zhang Xincheng <zhangxincheng@...rarisc.com>,
	Charlie Jenkins <charlie@...osinc.com>,
	Marc Zyngier <maz@...nel.org>,
	Sia Jee Heng <jeeheng.sia@...rfivetech.com>,
	Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Rob Herring <robh@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	Alexandre Ghiti <alex@...ti.fr>, devicetree@...r.kernel.org,
	Jia Wang <wangjia@...rarisc.com>
Subject: Re: [PATCH v3 2/2] dt-binding: riscv: Clarify the riscv,ndev meaning
 in PLIC

On Wed, Feb 04, 2026 at 01:21:48AM +0800, Yangyu Chen wrote:
> In PLIC, interrupt source 0 is reserved and should not be used.
> Therefore, the valid interrupt sources are from 1 to riscv,ndev
> inclusive. This commit updates the documentation to clarify this point.
> 
> Signed-off-by: Yangyu Chen <cyy@...self.name>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 388fc2c620c0..df9578bcac89 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -109,6 +109,8 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description:
>        Specifies how many external interrupts are supported by this controller.
> +      Note that source 0 is reserved in PLIC, so the valid interrupt sources
> +      are 1 to riscv,ndev inclusive.

The trm for mpfs says "in the plic, global interrupt id 0 means 'no
interrupt'". That sounds subtly different to me than "reserved", but
/shrug
I think this could just be truncated to "Valid interrupt sources are
1 to riscv,ndev, inclusive.".
Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)