Message-ID: <fbd47594-7404-4462-b5ff-3177eef465fa@intel.com>
Date: Wed, 4 Feb 2026 10:56:49 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Robert Richter <rrichter@....com>
Cc: Alison Schofield <alison.schofield@...el.com>,
 Vishal Verma <vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>,
 Dan Williams <dan.j.williams@...el.com>,
 Jonathan Cameron <jonathan.cameron@...wei.com>,
 Davidlohr Bueso <dave@...olabs.net>, linux-cxl@...r.kernel.org,
 linux-kernel@...r.kernel.org, Gregory Price <gourry@...rry.net>,
 "Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>,
 Terry Bowman <terry.bowman@....com>, Joshua Hahn <joshua.hahnjy@...il.com>
Subject: Re: [PATCH v9 00/13] cxl: ACPI PRM Address Translation Support and
 AMD Zen5 enablement



On 2/4/26 5:58 AM, Robert Richter wrote:
> Hi Dave,
> 
> On 03.02.26 11:52:02, Dave Jiang wrote:
>>
>>
>> On 1/10/26 4:46 AM, Robert Richter wrote:
>>> This patch set adds support for address translation using ACPI PRM and
>>> enables this for AMD Zen5 platforms. The current approach bases on v4
>>> and is in response to earlier attempts to implement CXL address
>>> translation:
>>>
>>>  * v1: [1] and the comments on it, esp. Dan's [2],
>>>  * v2: [3] and comments on [4], esp. Dave's [5],
>>>  * v3: [6] and comments on it, esp. Dave's [7],
>>>  * v4: [8].
>>>
>>> This version addresses Alison's review comments to change the
>>> implementation to disable HPA/SPA translation handler. There are a
>>> view minor but no major changes otherwise. See the changelog for
>>> details. Thank you all for your reviews and testing.
>>>
>>> Documentation of CXL Address Translation Support will be added to the
>>> Kernel's "Compute Express Link: Linux Conventions". This patch
>>> submission will be the base for a documentation patch that describes CXL
>>> Address Translation support accordingly.
>>>
>>> The CXL driver currently does not implement address translation which
>>> assumes the host physical addresses (HPA) and system physical
>>> addresses (SPA) are equal.
>>>
>>> Systems with different HPA and SPA addresses need address translation.
>>> If this is the case, the hardware addresses esp. used in the HDM
>>> decoder configurations are different to the system's or parent port
>>> address ranges. E.g. AMD Zen5 systems may be configured to use
>>> 'Normalized addresses'. Then, CXL endpoints have their own physical
>>> address base which is not the same as the SPA used by the CXL host
>>> bridge. Thus, addresses need to be translated from the endpoint's to
>>> its CXL host bridge's address range.
>>>
>>> To enable address translation, the endpoint's HPA range must be
>>> translated to the CXL host bridge's address range. A callback is
>>> introduced to translate a decoder's HPA to the CXL host bridge's
>>> address range. The callback is then used to determine the region
>>> parameters which includes the SPA translated address range of the
>>> endpoint decoder and the interleaving configuration. This is stored in
>>> struct cxl_region which allows an endpoint decoder to determine that
>>> parameters based on its assigned region.
>>>
>>> Note that only auto-discovery of decoders is supported. Thus, decoders
>>> are locked and cannot be configured manually.
>>>
>>> Finally, Zen5 address translation is enabled using ACPI PRMT.
>>>
>>> This series bases on v6.19-rc1.
>>
>> Applied to cxl/next. Including the conventions doc.
>> 00bc604c96bb762f0f050460e25de2729edb1699
> 
> Thank you for applying the series, I noticed wrong authorship of
> a0a135b410f57702ac6a463005c656f291eb7b90, could you fix that?

Sorry about that. Not sure how it happened. Fixed now. cxl/next repushed.
63fbf275fa9f18f7020fb8acf54fa107e51d0f23
> 
> Thank you,
> 
> -Robert

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