| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20260204180632.249139-6-biju.das.jz@bp.renesas.com>
Date: Wed, 4 Feb 2026 18:06:21 +0000
From: Biju <biju.das.au@...il.com>
To: Thomas Gleixner <tglx@...nel.org>
Cc: Biju Das <biju.das.jz@...renesas.com>,
linux-kernel@...r.kernel.org,
Geert Uytterhoeven <geert+renesas@...der.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
Biju Das <biju.das.au@...il.com>,
linux-renesas-soc@...r.kernel.org
Subject: [PATCH v2 5/9] irqchip/renesas-rzg2l: Drop IRQC_TINT_START macro
From: Biju Das <biju.das.jz@...renesas.com>
The IRQC_TINT_START value is different for RZ/G3L and RZ/G2L SoC. Add
tint_start variable in struct rzg2l_hw_info to handle this differences
and drop the macro IRQC_TINT_START.
Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
---
v1->v2:
* No change
---
drivers/irqchip/irq-renesas-rzg2l.c | 30 +++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index cd9909a85280..e5393306f610 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -22,7 +22,6 @@
#define IRQC_IRQ_START 1
#define IRQC_IRQ_COUNT 8
-#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
#define IRQC_TINT_COUNT 32
#define ISCR 0x10
@@ -69,9 +68,11 @@ struct rzg2l_irqc_reg_cache {
/**
* struct rzg2l_hw_info - Interrupt Control Unit controller hardware info structure.
+ * @tint_start: Start of TINT interrupts
* @num_irq: Total Number of interrupts
*/
struct rzg2l_hw_info {
+ u8 tint_start;
u8 num_irq;
};
@@ -123,7 +124,7 @@ static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq
static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info->tint_start);
u32 reg;
reg = readl_relaxed(priv->base + TSCR);
@@ -145,7 +146,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
raw_spin_lock(&priv->lock);
if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
rzg2l_clear_irq_int(priv, hw_irq);
- else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
+ else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
rzg2l_clear_tint_int(priv, hw_irq);
raw_spin_unlock(&priv->lock);
irq_chip_eoi_parent(d);
@@ -170,7 +171,7 @@ static void rzfive_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info->tint_start);
writel_relaxed(readl_relaxed(priv->base + TMSK) | bit, priv->base + TMSK);
}
@@ -178,7 +179,7 @@ static void rzfive_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
static void rzfive_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
unsigned int hwirq)
{
- u32 bit = BIT(hwirq - IRQC_TINT_START);
+ u32 bit = BIT(hwirq - priv->info->tint_start);
writel_relaxed(readl_relaxed(priv->base + TMSK) & ~bit, priv->base + TMSK);
}
@@ -191,7 +192,7 @@ static void rzfive_irqc_mask(struct irq_data *d)
raw_spin_lock(&priv->lock);
if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
rzfive_irqc_mask_irq_interrupt(priv, hwirq);
- else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
+ else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
rzfive_irqc_mask_tint_interrupt(priv, hwirq);
raw_spin_unlock(&priv->lock);
irq_chip_mask_parent(d);
@@ -205,7 +206,7 @@ static void rzfive_irqc_unmask(struct irq_data *d)
raw_spin_lock(&priv->lock);
if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
rzfive_irqc_unmask_irq_interrupt(priv, hwirq);
- else if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq)
+ else if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq)
rzfive_irqc_unmask_tint_interrupt(priv, hwirq);
raw_spin_unlock(&priv->lock);
irq_chip_unmask_parent(d);
@@ -216,8 +217,8 @@ static void rzfive_tint_irq_endisable(struct irq_data *d, bool enable)
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
- if (hwirq >= IRQC_TINT_START && hwirq < priv->info->num_irq) {
- u32 offset = hwirq - IRQC_TINT_START;
+ if (hwirq >= priv->info->tint_start && hwirq < priv->info->num_irq) {
+ u32 offset = hwirq - priv->info->tint_start;
u32 tssr_offset = TSSR_OFFSET(offset);
u8 tssr_index = TSSR_INDEX(offset);
u32 reg;
@@ -261,9 +262,9 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hw_irq = irqd_to_hwirq(d);
- if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq) {
+ if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq) {
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
- u32 offset = hw_irq - IRQC_TINT_START;
+ u32 offset = hw_irq - priv->info->tint_start;
u32 tssr_offset = TSSR_OFFSET(offset);
u8 tssr_index = TSSR_INDEX(offset);
u32 reg;
@@ -354,7 +355,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
{
struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
unsigned int hwirq = irqd_to_hwirq(d);
- u32 titseln = hwirq - IRQC_TINT_START;
+ u32 titseln = hwirq - priv->info->tint_start;
u32 tssr_offset = TSSR_OFFSET(titseln);
u8 tssr_index = TSSR_INDEX(titseln);
u8 index, sense;
@@ -401,7 +402,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
ret = rzg2l_irq_set_type(d, type);
- else if (hw_irq >= IRQC_TINT_START && hw_irq < priv->info->num_irq)
+ else if (hw_irq >= priv->info->tint_start && hw_irq < priv->info->num_irq)
ret = rzg2l_tint_set_edge(d, type);
if (ret)
return ret;
@@ -503,7 +504,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
tint = TINT_EXTRACT_GPIOINT(hwirq);
hwirq = TINT_EXTRACT_HWIRQ(hwirq);
- if (hwirq < IRQC_TINT_START)
+ if (hwirq < priv->info->tint_start)
return -EINVAL;
}
@@ -606,6 +607,7 @@ static int rzg2l_irqc_common_probe(struct platform_device *pdev, struct device_n
}
static const struct rzg2l_hw_info rzg2l_hw_params = {
+ .tint_start = IRQC_IRQ_START + IRQC_IRQ_COUNT,
.num_irq = IRQC_IRQ_START + IRQC_IRQ_COUNT + IRQC_TINT_COUNT,
};
--
2.43.0
Powered by blists - more mailing lists