linux-kernel - RE: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID:
 <MN0PR12MB59537BC8B60D76CCE0B1391CB798A@MN0PR12MB5953.namprd12.prod.outlook.com>
Date: Wed, 4 Feb 2026 08:32:02 +0000
From: "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>
To: Sean Anderson <sean.anderson@...ux.dev>, Laurent Pinchart
	<laurent.pinchart@...asonboard.com>, Vinod Koul <vkoul@...nel.org>,
	"linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>
CC: Krzysztof Wilczyński <kwilczynski@...nel.org>, Lorenzo
 Pieralisi <lpieralisi@...nel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "Simek, Michal" <michal.simek@....com>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, Neil Armstrong <neil.armstrong@...aro.org>, Rob
 Herring <robh@...nel.org>, "Havalige, Thippeswamy"
	<thippeswamy.havalige@....com>, Manivannan Sadhasivam <mani@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>, Conor Dooley <conor+dt@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>
Subject: RE: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Sean Anderson <sean.anderson@...ux.dev>
> Sent: Tuesday, February 3, 2026 5:51 AM
> To: Laurent Pinchart <laurent.pinchart@...asonboard.com>; Vinod Koul
> <vkoul@...nel.org>; linux-phy@...ts.infradead.org
> Cc: Krzysztof Wilczyński <kwilczynski@...nel.org>; Lorenzo Pieralisi
> <lpieralisi@...nel.org>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@....com>; linux-kernel@...r.kernel.org; Simek, Michal
> <michal.simek@....com>; linux-arm-kernel@...ts.infradead.org; linux-
> pci@...r.kernel.org; Neil Armstrong <neil.armstrong@...aro.org>; Rob Herring
> <robh@...nel.org>; Havalige, Thippeswamy <thippeswamy.havalige@....com>;
> Manivannan Sadhasivam <mani@...nel.org>; Bjorn Helgaas
> <bhelgaas@...gle.com>; Sean Anderson <sean.anderson@...ux.dev>; Conor
> Dooley <conor+dt@...nel.org>; Krzysztof Kozlowski <krzk+dt@...nel.org>;
> devicetree@...r.kernel.org
> Subject: [PATCH 1/8] dt-bindings: pci: xilinx-nwl: Add resets
>
> Add resets so we can hold the bridge in reset while we perform phy calibration.

Seems like this should a required property?

Rest looks fine to me.

>
> Signed-off-by: Sean Anderson <sean.anderson@...ux.dev>
> ---
>
>  .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml  | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 9de3c09efb6e..7efb3dd9955f 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -69,6 +69,18 @@ properties:
>    power-domains:
>      maxItems: 1
>
> +  resets:
> +    maxItems: 3
> +
> +  reset-names:
> +    items:
> +      - description: APB register block reset
> +        const: cfg
> +      - description: AXI-PCIe bridge reset
> +        const: bridge
> +      - description: PCIe MAC reset
> +        const: ctrl
> +
>    iommus:
>      maxItems: 1
>
> @@ -117,6 +129,7 @@ examples:
>      #include <dt-bindings/interrupt-controller/irq.h>
>      #include <dt-bindings/phy/phy.h>
>      #include <dt-bindings/power/xlnx-zynqmp-power.h>
> +    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
>      soc {
>          #address-cells = <2>;
>          #size-cells = <2>;
> @@ -146,6 +159,10 @@ examples:
>              msi-parent = <&nwl_pcie>;
>              phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
>              power-domains = <&zynqmp_firmware PD_PCIE>;
> +            resets = <&zynqmp_reset ZYNQMP_RESET_PCIE_CFG>,
> +                     <&zynqmp_reset ZYNQMP_RESET_PCIE_BRIDGE>,
> +                     <&zynqmp_reset ZYNQMP_RESET_PCIE_CTRL>;
> +            reset-names = "cfg", "bridge", "ctrl";
>              iommus = <&smmu 0x4d0>;
>              pcie_intc: legacy-interrupt-controller {
>                  interrupt-controller;
> --
> 2.35.1.1320.gc452695387.dirty