| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <aYQPPv-J5qWDRSXd@lizhi-Precision-Tower-5810>
Date: Wed, 4 Feb 2026 22:32:14 -0500
From: Frank Li <Frank.li@....com>
To: Tim Harvey <tharvey@...eworks.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] arm64: dts: imx: Add i.mx8mm Gateworks GW7906 dts
support
On Wed, Feb 04, 2026 at 02:50:20PM -0800, Tim Harvey wrote:
> The GW7906 is based on the i.MX8M Mini SoC featuring:
> - LPDDR4 DRAM
> - eMMC FLASH
> - microSD connector with UHS support
> - LIS2DE12 3-axis accelerometer
> - Gateworks System Controller
> - IMX8M FEC
> - software selectable RS232/RS485/RS422 serial transceiver
> - PMIC
> - 1x isolated RS232 UART
> - 1x off-board bi-directional opto-isolated digital I/O
> - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe
> (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket)
>
> The GW7906 has much in common with the GW7903 so it is used as a base.
> Differences include:
> - different GbE PHY
> - a couple of new GPIO's added
> - removal of uart1
> - removal of io-expander
>
> Signed-off-by: Tim Harvey <tharvey@...eworks.com>
> ---
> v2:
> - ran through dt-format
Thanks
> - use gw7903 as a base due to little difference in boards
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx8mm-venice-gw7906.dts | 92 +++++++++++++++++++
> 2 files changed, 93 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7906.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 700bab4d3e60..83fc7faf81d8 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -167,6 +167,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7906.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7906.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7906.dts
> new file mode 100644
> index 000000000000..c4d0610e34ab
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7906.dts
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2026 Gateworks Corporation
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +#include "imx8mm-venice-gw7903.dts"
In
https://lore.kernel.org/imx/20260123-gifted-wolverine-from-mars-47b9d4@quoll/
don't prefer dts include dts.
Can you create common dtsi?
then both mx8mm-venice-gw7906.dts and mx8mm-venice-gw7903.dts include
this common dtsi.
Ref the method at
https://lore.kernel.org/imx/20260204083551.2867263-6-sherry.sun@nxp.com/
Frank
> +
> +/ {
> + compatible = "gateworks,imx8mm-gw7906", "fsl,imx8mm";
> + model = "Gateworks Venice GW7906 i.MX8MM board";
> +};
> +
> +&fec1 {
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> +
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@1 {
> + reg = <1>;
> + color = <LED_COLOR_ID_AMBER>;
> + default-state = "keep";
> + function = LED_FUNCTION_LAN;
> + };
> +
> + led@2 {
> + reg = <2>;
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "keep";
> + function = LED_FUNCTION_LAN;
> + };
> + };
> + };
> + };
> +};
> +
> +&gpio2 {
> + gpio-line-names = "", "", "", "", "", "", "dig1_ctl", "",
> + "dig1_out#", "dig1_in", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&gpio5 {
> + gpio-line-names = "iob", "ioa", "", "", "", "", "", "",
> + "", "", "", "", "pci_wdis#", "", "", "",
> + "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "";
> +};
> +
> +&i2c1 {
> + /delete-node/ gpio@27;
> +};
> +
> +&iomuxc {
> + pinctrl-0 = <&pinctrl_hog>;
> + pinctrl-names = "default";
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
> + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
> + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
> + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
> + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
> + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40000041 /* DIG1_CTL */
> + MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
> + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x40000041 /* IOA */
> + MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x40000041 /* IOB */
> + >;
> + };
> +};
> +
> +&uart1 {
> + status = "disabled";
> +};
> --
> 2.25.1
>
Powered by blists - more mailing lists