Message-Id: <20260205-schneider-6-19-rc1-qspi-v5-0-843632b3c674@bootlin.com>
Date: Thu, 05 Feb 2026 19:09:47 +0100
From: "Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
To: Mark Brown <broonie@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Geert Uytterhoeven <geert+renesas@...der.be>, 
 Magnus Damm <magnus.damm@...il.com>, Vaishnav Achath <vaishnav.a@...com>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, 
 Hervé Codina <herve.codina@...tlin.com>, 
 Wolfram Sang <wsa+renesas@...g-engineering.com>, 
 Vignesh Raghavendra <vigneshr@...com>, Santhosh Kumar K <s-k6@...com>, 
 Pratyush Yadav <pratyush@...nel.org>, 
 Pascal Eberhard <pascal.eberhard@...com>, linux-spi@...r.kernel.org, 
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
 linux-renesas-soc@...r.kernel.org, 
 "Miquel Raynal (Schneider Electric)" <miquel.raynal@...tlin.com>
Subject: [PATCH v5 0/4] spi: cadence-qspi: Add Renesas RZ/N1 support

Hello,

This series adds support for the QSPI controller available on Renesas
RZ/N1S and RZ/N1D SoC. It has been tested with a custom board (see last
SPI patch for details), but has been tested by Wolfram (thank you!) on
the DB board.
Link: https://lore.kernel.org/linux-devicetree/20260116114852.52948-2-wsa+renesas@sang-engineering.com/

Adding support for this SoC required a few adaptations to the Cadence
QSPI driver which have already been merged (except one regarding clocks
handling). This series contains the remaining patches, the ones actually
adding support for the RZ/N1 flavour.

Thanks,
Miquèl

Signed-off-by: Miquel Raynal (Schneider Electric) <miquel.raynal@...tlin.com>
---
Changes in v5:
- Rebased on top of spi/for-next, fixed the binding conflict manually.
- Fixed the name of the SoC, as reported by Geert.
- Link to v4: https://lore.kernel.org/r/20260122-schneider-6-19-rc1-qspi-v4-0-f9c21419a3e6@bootlin.com

Changes in v4:
- Drop two binding patches judged useless.
- Collected Rob's acks.
- Fixed the RZ/N1D400 DTSI (removed the properties no longer relevant
  after my binding changes).
- Link to v3: https://lore.kernel.org/r/20260121-schneider-6-19-rc1-qspi-v3-0-43e70fab4444@bootlin.com

Changes in v3:
- Collected tags from Wolfram and Geert.
- Dropped the Cadence compatible as this fallback would simply not work
  alone.
- Fixed the clock issue reported by Santhosh.
- Fixed the DT snippet following the discussion with Geert.
- Modified more deeply the binding, to no longer expect a fifo
  size/depth nor any trigger address, as these values have no meaning in
  the score of the Renesas implementation.
- Link to v2: https://lore.kernel.org/r/20260115-schneider-6-19-rc1-qspi-v2-0-7e6a06e1e17b@bootlin.com

Changes in v2:
- Fix commit log of DT binding patch, following Krzysztof's comment.
- Fix properties order in DTSI.
- Rebase on top of spi/for-next and fix all conflicts.
- Simplify even further the code in the cleanup patches following
  Pratyush's advices.
- Link to v1: https://lore.kernel.org/r/20251219-schneider-6-19-rc1-qspi-v1-0-8ad505173e44@bootlin.com

---
Miquel Raynal (Schneider Electric) (4):
      spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
      spi: cadence-qspi: Kill cqspi_jh7110_clk_init
      spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
      ARM: dts: r9a06g032: Describe the QSPI controller

 .../devicetree/bindings/spi/cdns,qspi-nor.yaml     |  19 ++-
 arch/arm/boot/dts/renesas/r9a06g032.dtsi           |  12 ++
 drivers/spi/spi-cadence-quadspi.c                  | 168 +++++++++------------
 3 files changed, 100 insertions(+), 99 deletions(-)
---
base-commit: d248c6d8d9eadcbf60345dc9cd924dc6cc4d9b44
change-id: 20251219-schneider-6-19-rc1-qspi-7c3e1547af6d

Best regards,
-- 
Miquel Raynal <miquel.raynal@...tlin.com>

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