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Message-Id: <20260205-zcull3-v2-1-ac572f38cc7b@darkrefraction.com>
Date: Thu, 05 Feb 2026 13:56:10 -0500
From: Mel Henning <mhenning@...krefraction.com>
To: Lyude Paul <lyude@...hat.com>, Danilo Krummrich <dakr@...nel.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Mary Guillemard <mary@...y.zone>
Cc: dri-devel@...ts.freedesktop.org, nouveau@...ts.freedesktop.org,
linux-kernel@...r.kernel.org, Mel Henning <mhenning@...krefraction.com>
Subject: [PATCH v2 1/2] drm/nouveau: Fetch zcull info from device
This information will be exposed to userspace in the following commit.
Signed-off-by: Mel Henning <mhenning@...krefraction.com>
---
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 19 +++++++++++++
.../gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c | 9 ++++--
.../gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c | 32 ++++++++++++++++++++--
.../drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h | 19 +++++++++++++
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h | 2 +-
5 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
index a2333cfe6955..490ce410f6cb 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
@@ -3,9 +3,28 @@
#define __NVKM_GR_H__
#include <core/engine.h>
+struct nvkm_gr_zcull_info {
+ __u32 width_align_pixels;
+ __u32 height_align_pixels;
+ __u32 pixel_squares_by_aliquots;
+ __u32 aliquot_total;
+ __u32 zcull_region_byte_multiplier;
+ __u32 zcull_region_header_size;
+ __u32 zcull_subregion_header_size;
+ __u32 subregion_count;
+ __u32 subregion_width_align_pixels;
+ __u32 subregion_height_align_pixels;
+
+ __u32 ctxsw_size;
+ __u32 ctxsw_align;
+};
+
struct nvkm_gr {
const struct nvkm_gr_func *func;
struct nvkm_engine engine;
+
+ struct nvkm_gr_zcull_info zcull_info;
+ bool has_zcull_info;
};
u64 nvkm_gr_units(struct nvkm_gr *);
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
index ddb57d5e73d6..73844e1e7294 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gr.c
@@ -249,7 +249,7 @@ r535_gr_get_ctxbuf_info(struct r535_gr *gr, int i,
}
static int
-r535_gr_get_ctxbufs_info(struct r535_gr *gr)
+r535_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr)
{
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
@@ -265,6 +265,9 @@ r535_gr_get_ctxbufs_info(struct r535_gr *gr)
r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine[i]);
nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info);
+
+ gr->base.has_zcull_info = false;
+
return 0;
}
@@ -312,7 +315,7 @@ r535_gr_oneinit(struct nvkm_gr *base)
*
* Also build the information that'll be used to create channel contexts.
*/
- ret = rm->api->gr->get_ctxbufs_info(gr);
+ ret = rm->api->gr->get_ctxbufs_and_zcull_info(gr);
if (ret)
goto done;
@@ -352,5 +355,5 @@ r535_gr_dtor(struct nvkm_gr *base)
const struct nvkm_rm_api_gr
r535_gr = {
- .get_ctxbufs_info = r535_gr_get_ctxbufs_info,
+ .get_ctxbufs_and_zcull_info = r535_gr_get_ctxbufs_and_zcull_info,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
index b6cced9b8aa1..3e7af2ffece9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/gr.c
@@ -164,9 +164,10 @@ r570_gr_scrubber_init(struct r535_gr *gr)
}
static int
-r570_gr_get_ctxbufs_info(struct r535_gr *gr)
+r570_gr_get_ctxbufs_and_zcull_info(struct r535_gr *gr)
{
NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS *info;
+ NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS *zcull_info;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_gsp *gsp = subdev->device->gsp;
@@ -179,13 +180,40 @@ r570_gr_get_ctxbufs_info(struct r535_gr *gr)
for (int i = 0; i < ARRAY_SIZE(info->engineContextBuffersInfo[0].engine); i++)
r535_gr_get_ctxbuf_info(gr, i, &info->engineContextBuffersInfo[0].engine[i]);
+ NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO zcull = info->engineContextBuffersInfo[0]
+ .engine[NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_GRAPHICS_ZCULL];
+ gr->base.zcull_info.ctxsw_size = zcull.size;
+ gr->base.zcull_info.ctxsw_align = zcull.alignment;
+
nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, info);
+
+ zcull_info = nvkm_gsp_rm_ctrl_rd(&gsp->internal.device.subdevice,
+ NV2080_CTRL_CMD_GR_GET_ZCULL_INFO,
+ sizeof(*zcull_info));
+ if (WARN_ON(IS_ERR(zcull_info)))
+ return PTR_ERR(zcull_info);
+
+ gr->base.zcull_info.width_align_pixels = zcull_info->widthAlignPixels;
+ gr->base.zcull_info.height_align_pixels = zcull_info->heightAlignPixels;
+ gr->base.zcull_info.pixel_squares_by_aliquots = zcull_info->pixelSquaresByAliquots;
+ gr->base.zcull_info.aliquot_total = zcull_info->aliquotTotal;
+ gr->base.zcull_info.zcull_region_byte_multiplier = zcull_info->zcullRegionByteMultiplier;
+ gr->base.zcull_info.zcull_region_header_size = zcull_info->zcullRegionHeaderSize;
+ gr->base.zcull_info.zcull_subregion_header_size = zcull_info->zcullSubregionHeaderSize;
+ gr->base.zcull_info.subregion_count = zcull_info->subregionCount;
+ gr->base.zcull_info.subregion_width_align_pixels = zcull_info->subregionWidthAlignPixels;
+ gr->base.zcull_info.subregion_height_align_pixels = zcull_info->subregionHeightAlignPixels;
+
+ nvkm_gsp_rm_ctrl_done(&gsp->internal.device.subdevice, zcull_info);
+
+ gr->base.has_zcull_info = true;
+
return 0;
}
const struct nvkm_rm_api_gr
r570_gr = {
- .get_ctxbufs_info = r570_gr_get_ctxbufs_info,
+ .get_ctxbufs_and_zcull_info = r570_gr_get_ctxbufs_and_zcull_info,
.scrubber.init = r570_gr_scrubber_init,
.scrubber.fini = r570_gr_scrubber_fini,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h
index feed1dabd9d2..a7a15a4de9d5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/nvrm/gr.h
@@ -76,4 +76,23 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_CMD_GR_GET_ZCULL_INFO (0x20801206U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
+
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_SUBREGION_SUPPORTED
+#define NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x6U)
+
+typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS {
+ NvU32 widthAlignPixels;
+ NvU32 heightAlignPixels;
+ NvU32 pixelSquaresByAliquots;
+ NvU32 aliquotTotal;
+ NvU32 zcullRegionByteMultiplier;
+ NvU32 zcullRegionHeaderSize;
+ NvU32 zcullSubregionHeaderSize;
+ NvU32 subregionCount;
+ NvU32 subregionWidthAlignPixels;
+ NvU32 subregionHeightAlignPixels;
+} NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS;
+
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
index 393ea775941f..0fb0e67406c6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
@@ -124,7 +124,7 @@ struct nvkm_rm_api {
} *ce, *nvdec, *nvenc, *nvjpg, *ofa;
const struct nvkm_rm_api_gr {
- int (*get_ctxbufs_info)(struct r535_gr *);
+ int (*get_ctxbufs_and_zcull_info)(struct r535_gr *);
struct {
int (*init)(struct r535_gr *);
void (*fini)(struct r535_gr *);
--
2.52.0
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