linux-kernel - Re: [PATCH v15 5/9] PCI: Establish common CXL Port protocol error flow

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Message-ID: <69850901d28f1_55fa100f5@dwillia2-mobl4.notmuch>
Date: Thu, 5 Feb 2026 13:17:53 -0800
From: <dan.j.williams@...el.com>
To: "Bowman, Terry" <terry.bowman@....com>, <dan.j.williams@...el.com>,
	<dave@...olabs.net>, <jonathan.cameron@...wei.com>, <dave.jiang@...el.com>,
	<alison.schofield@...el.com>, <bhelgaas@...gle.com>, <shiju.jose@...wei.com>,
	<ming.li@...omail.com>, <Smita.KoralahalliChannabasappa@....com>,
	<rrichter@....com>, <dan.carpenter@...aro.org>,
	<PradeepVineshReddy.Kodamati@....com>, <lukas@...ner.de>,
	<Benjamin.Cheatham@....com>, <sathyanarayanan.kuppuswamy@...ux.intel.com>,
	<linux-cxl@...r.kernel.org>, <vishal.l.verma@...el.com>, <alucerop@....com>,
	<ira.weiny@...el.com>
CC: <linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>
Subject: Re: [PATCH v15 5/9] PCI: Establish common CXL Port protocol error
 flow

Bowman, Terry wrote:
[..]
> > The answer that feels consistent with unburdening the PCI core with the
> > vagaries CXL is to include RCH errors in the class of notifications that
> > get forwarded. Arrange for cxl_proto_err_work_data to carry whether it
> > is an RCH or VH error and then dispatch either
> > cxl_handle_rdport_errors() or cxl_handle_proto_error().
> 
> 
> That approach makes sense to me.
> 
> Would you like to keep the RCH's RCiEP traversal in the AER driver for now? In
> that model, the RCiEP PCI device ID would be passed via cxl_proto_err_work_data. 
> This would be a relatively small change — updating cxl_rch_handle_error_iter() 
> and pcie/aer_cxl_rch.c to call cxl_forward_error().
> 
> A cleaner long-term approach would be to move all of the logic in aer_cxl_rch.c 
> into cxl/core/rch_ras.c. In that case, an RCEC (reporting on behalf of the RCH 
> error) would be passed in cxl_proto_err_work_data, and RCiEP iteration would be 
> handled by the CXL driver after the work item surfaces from the kfifo.
> 
> The second approach improves PCI/CXL separation, but it may be harder to land 
> late in the series. Would it be acceptable to proceed with the first approach 
> initially, followed immediately by a cleanup series moving pcie/aer_cxl_rch.c 
> into cxl/core/rch_ras.c?

I think it is fine to do this incrementally. Keep RCiEP traversal in AER
for now. Later move more of that logic to the CXL core so PCI does not
need to worry about that complication. That later move makes it easier
to add consideration for details like the "RCEC Downstream Port
Association Structure" (RDPAS) without thrashing the PCI core.