linux-kernel - [PATCH 3/3] arm64: dts: rockchip: Enable OTP controller for RK3528

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Message-ID: <20260205212347.490636-4-heiko@sntech.de>
Date: Thu,  5 Feb 2026 22:23:47 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: heiko@...ech.de
Cc: linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	kever.yang@...k-chips.com,
	finley.xiao@...k-chips.com,
	w@....eu,
	jonas@...boo.se
Subject: [PATCH 3/3] arm64: dts: rockchip: Enable OTP controller for RK3528

From: Jonas Karlman <jonas@...boo.se>

Enable the One Time Programmable Controller (OTPC) in RK3528 and add
an initial nvmem fixed layout.

Signed-off-by: Jonas Karlman <jonas@...boo.se>
Signed-off-by: Heiko Stuebner <heiko@...ech.de>
---
 arch/arm64/boot/dts/rockchip/rk3528.dtsi | 47 ++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index d402f2828814..171b48c9cdb7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -1190,6 +1190,53 @@ sdmmc: mmc@...30000 {
 			status = "disabled";
 		};
 
+		otp: nvmem@...e0000 {
+			compatible = "rockchip,rk3528-otp";
+			reg = <0x0 0xffce0000 0x0 0x4000>;
+			clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+				 <&cru CLK_SBPI_OTPC_NS>;
+			clock-names = "otp", "apb_pclk", "sbpi";
+			resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
+				 <&cru SRST_SBPI_OTPC_NS>;
+			reset-names = "otp", "apb", "sbpi";
+
+			nvmem-layout {
+				compatible = "fixed-layout";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				cpu_code: cpu-code@2 {
+					reg = <0x02 0x2>;
+				};
+
+				otp_cpu_version: cpu-version@8 {
+					reg = <0x08 0x1>;
+					bits = <3 3>;
+				};
+
+				otp_id: id@a {
+					reg = <0x0a 0x10>;
+				};
+
+				cpu_leakage: cpu-leakage@1a {
+					reg = <0x1a 0x1>;
+				};
+
+				logic_leakage: logic-leakage@1b {
+					reg = <0x1b 0x1>;
+				};
+
+				gpu_leakage: gpu-leakage@1c {
+					reg = <0x1c 0x1>;
+				};
+
+				tsadc_trim: tsadc-trim@44 {
+					reg = <0x44 0x2>;
+					bits = <0 10>;
+				};
+			};
+		};
+
 		dmac: dma-controller@...60000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x0 0xffd60000 0x0 0x4000>;
-- 
2.47.2