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Message-Id: <20260205010502.2554381-1-xujiakai2025@iscas.ac.cn>
Date: Thu, 5 Feb 2026 01:05:00 +0000
From: Jiakai Xu <xujiakai2025@...as.ac.cn>
To: linux-kernel@...r.kernel.org,
kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org,
linux-riscv@...ts.infradead.org,
linux-kselftest@...r.kernel.org
Cc: Anup Patel <anup@...infault.org>,
Atish Patra <atish.patra@...ux.dev>,
Paul Walmsley <pjw@...nel.org>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Andrew Jones <ajones@...tanamicro.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Shuah Khan <shuah@...nel.org>,
Jiakai Xu <xujiakai2025@...as.ac.cn>
Subject: [PATCH v6 0/2] RISC-V: KVM: Validate SBI STA shmem alignment
This series fixes a missing validation in the RISC-V KVM SBI
steal-time accounting (STA) register handling.
Patch 1 validates the configured SBI STA shared memory GPA at
KVM_SET_ONE_REG, enforcing the 64-byte alignment requirement
defined by the SBI specification or allowing INVALID_GPA to explicitly
disable steal-time accounting. This prevents invalid userspace state
from reaching runtime code paths and avoids WARN_ON() triggers during
KVM_RUN.
Patch 2 adds RISC-V KVM selftests to verify the expected behavior,
ensuring that misaligned GPAs are rejected, aligned GPAs are accepted,
and INVALID_GPA correctly disables steal-time accounting.
Jiakai Xu (2):
RISC-V: KVM: Validate SBI STA shmem alignment in
kvm_sbi_ext_sta_set_reg()
RISC-V: KVM: selftests: Add RISC-V SBI STA shmem alignment tests
arch/riscv/kvm/vcpu_sbi_sta.c | 16 ++++++---
.../selftests/kvm/include/riscv/processor.h | 4 +++
tools/testing/selftests/kvm/steal_time.c | 33 +++++++++++++++++++
3 files changed, 48 insertions(+), 5 deletions(-)
--
2.34.1
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