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Message-ID: <c233610d-2edd-44ab-9f96-7312312d756c@leica-geosystems.com>
Date: Thu, 5 Feb 2026 09:58:20 +0000
From: PETER Mario <mario.peter@...ca-geosystems.com>
To: Ahmad Fatoum <a.fatoum@...gutronix.de>, "shawnguo@...nel.org"
<shawnguo@...nel.org>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>
CC: "robh@...nel.org" <robh@...nel.org>, "conor+dt@...nel.org"
<conor+dt@...nel.org>, "devicetree@...r.kernel.org"
<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, "imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"kernel@...gutronix.de" <kernel@...gutronix.de>, "krzk+dt@...nel.org"
<krzk+dt@...nel.org>, "festevam@...il.com" <festevam@...il.com>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v1] arm64: dts: freescale: imx8mm-evk: share usdhc3 setup
On 2/3/26 15:36, Ahmad Fatoum wrote:
> [You don't often get email from a.fatoum@...gutronix.de. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
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>
>
> Hello Mario,
>
> thanks for your patch.
>
> On 2/3/26 3:21 PM, Mario Peter wrote:
>> The eMMC controller on EVK and EVKB uses the same usdhc3
>> configuration and pinmux. Move the common node and pinctrl groups
>> into imx8mm-evk.dtsi so both boards inherit the shared setup and
>> avoid duplication in the board DTS files.
>
> What about the imx8mm-ddr4-evk.dts? Did you check if it also has
> something connected to usdhc3?
>
> Cheers,
> Ahmad
>
Hi Ahmad,
Thanks for the review. That's a good catch. The imx8mm-ddr4-evk uses GPMI
NAND on those pins instead of usdhc3, so moving this to the shared .dtsi
would break that variant.
Please disregard this patch.
Best regards,
Mario
>>
>> Signed-off-by: Mario Peter <mario.peter@...ca-geosystems.com>
>> ---
>> v1: submitted
>>
>> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 61 -------------------
>> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 61 +++++++++++++++++++
>> 2 files changed, 61 insertions(+), 61 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> index b68954bcc383..002ebdeeb2d6 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> @@ -53,18 +53,6 @@ flash@0 {
>> };
>> };
>>
>> -&usdhc3 {
>> - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
>> - assigned-clock-rates = <400000000>;
>> - pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> - pinctrl-0 = <&pinctrl_usdhc3>;
>> - pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>> - pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
>> - bus-width = <8>;
>> - non-removable;
>> - status = "okay";
>> -};
>> -
>> &iomuxc {
>> pinctrl_flexspi: flexspigrp {
>> fsl,pins = <
>> @@ -76,53 +64,4 @@ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
>> MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>> >;
>> };
>> -
>> - pinctrl_usdhc3: usdhc3grp {
>> - fsl,pins = <
>> - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
>> - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>> - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
>> - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
>> - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
>> - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
>> - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
>> - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
>> - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
>> - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
>> - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
>> - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>> - >;
>> - };
>> -
>> - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>> - fsl,pins = <
>> - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
>> - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>> - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
>> - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
>> - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
>> - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
>> - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
>> - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
>> - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
>> - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
>> - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>> - >;
>> - };
>> -
>> - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>> - fsl,pins = <
>> - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
>> - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>> - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
>> - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
>> - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
>> - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
>> - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
>> - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
>> - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
>> - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
>> - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>> - >;
>> - };
>> };
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> index 6eab8a6001db..6e53828b5d30 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> @@ -649,6 +649,18 @@ &usdhc2 {
>> status = "okay";
>> };
>>
>> +&usdhc3 {
>> + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
>> + assigned-clock-rates = <400000000>;
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc3>;
>> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + status = "okay";
>> +};
>> +
>> &wdog1 {
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_wdog>;
>> @@ -839,6 +851,55 @@ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> >;
>> };
>>
>> + pinctrl_usdhc3: usdhc3grp {
>> + fsl,pins = <
>> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
>> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
>> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
>> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
>> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
>> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
>> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
>> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
>> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
>> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
>> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
>> + fsl,pins = <
>> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
>> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
>> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
>> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
>> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
>> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
>> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
>> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
>> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
>> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>> + >;
>> + };
>> +
>> + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
>> + fsl,pins = <
>> + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
>> + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>> + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
>> + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
>> + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
>> + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
>> + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
>> + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
>> + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
>> + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
>> + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>> + >;
>> + };
>> +
>> pinctrl_wdog: wdoggrp {
>> fsl,pins = <
>> MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>
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