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Message-ID: <20260205102104.394991-3-heiko@sntech.de>
Date: Thu, 5 Feb 2026 11:21:03 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: heiko@...ech.de
Cc: quentin.schulz@...rry.de,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: [PATCH 2/3] arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger
From: Heiko Stuebner <heiko.stuebner@...rry.de>
Using a combination of fixed clock and gpio-gate clock works but does
not describe the actual hardware. Use the gated-fixed-clock binding
to describe this in a nicer way.
Signed-off-by: Heiko Stuebner <heiko.stuebner@...rry.de>
---
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
index 27269b7b08aa..259fb125e13f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
@@ -51,19 +51,14 @@ led-1 {
* 100MHz reference clock for PCIe peripherals from PI6C557-05BLE
* clock generator.
* The clock output is gated via the OE pin on the clock generator.
- * This is modeled as a fixed-clock plus a gpio-gate-clock.
*/
- pcie_refclk_gen: pcie-refclk-gen-clock {
- compatible = "fixed-clock";
+ pcie_refclk: pcie-clock-generator {
+ compatible = "gated-fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
- };
-
- pcie_refclk: pcie-refclk-clock {
- compatible = "gpio-gate-clock";
- clocks = <&pcie_refclk_gen>;
- #clock-cells = <0>;
+ clock-output-names = "pcie3_refclk";
enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */
+ vdd-supply = <&vcca_3v3_s0>;
};
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
--
2.47.2
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