linux-kernel - Re: [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account for the MX domain

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Message-ID: <mlpe7ph27grv4bulvwlo5lbbsjmwqqfwc3rrfwfcu7tl7qltsu@xrtzonb2t44k>
Date: Thu, 5 Feb 2026 14:48:14 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Taniya Das <quic_tdas@...cinc.com>,
        Jonathan Marek <jonathan@...ek.ca>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Bryan O'Donoghue <bod@...nel.org>,
        Vikash Garodia <vikash.garodia@....qualcomm.com>,
        Dikshita Agarwal <dikshita.agarwal@....qualcomm.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Stanimir Varbanov <stanimir.varbanov@...aro.org>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Hans Verkuil <hverkuil@...nel.org>,
        Stefan Schmidt <stefan.schmidt@...aro.org>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
        Dikshita Agarwal <dikshita@....qualcomm.com>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-pm@...r.kernel.org, linux-media@...r.kernel.org,
        Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
Subject: Re: [PATCH v3 1/7] dt-bindings: clock: qcom,sm8250-videocc: account
 for the MX domain

On Thu, Feb 05, 2026 at 12:31:54PM +0100, Krzysztof Kozlowski wrote:
> On Wed, Feb 04, 2026 at 02:59:49AM +0200, Dmitry Baryshkov wrote:
> > To configure the video PLLs and enable the video GDSCs on SM8250,
> > platform, the MX rail must be ON along with MMCX. Split the bindings
> > file in order to provide separate file utilizing MMCX and MX power
> > domains.
> 
> ...
> 
> > +
> > +description: |
> > +  Qualcomm video clock control module provides the clocks, resets and power
> > +  domains on Qualcomm SoCs.
> > +
> > +  See also::
> 
> Only one ':', please. It was a mistake to introduce ::

Ack.

> 
> > +  clock-names:
> > +    items:
> > +      - const: iface
> > +      - const: bi_tcxo
> > +      - const: bi_tcxo_ao
> > +
> > +  power-domains:
> > +    items:
> > +      - description:
> > +          A phandle and PM domain specifier for the MMCX power domain.
> > +      - description:
> > +          A phandle and PM domain specifier for the MX power domain.
> 
> This is an ABI break, so please say in the commit what was not working
> or why this ABI break is really justified. Currently you just give a
> hint that it is needed for PLL configuration, but honestly - why would
> we care to configure PLL if everything was working correct before?

I must admit, I c&p'ed the commit message from [1] which was ack'ed by
Rob and accepted into the kernel. What is the difference?

[1] https://lore.kernel.org/all/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com/

-- 
With best wishes
Dmitry