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Message-ID: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com>
Date: Thu, 5 Feb 2026 18:23:38 -0600
From: Andrew Jones <andrew.jones@....qualcomm.com>
To: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
kvm-riscv@...ts.infradead.org
Cc: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
Clément Léger <cleger@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Guodong Xu <guodong@...cstar.com>,
Charlie Jenkins <charlie@...osinc.com>,
Charlie Jenkins <thecharlesjenkins@...il.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior
Users need a way determine that their harts conform to rva23u64 that
isn't error-prone. While patches 2 and 6 make it possible to determine,
it requires a bunch of probes and checks themselves (see patch9 for the
recipe). This RFC proposes adding an RVA23U64 hwprobe base behavior
(patch8) allowing easy determination. It also proposes adding the bases
to /proc/cpuinfo (patches 10 and 11) -- but those two patches are probably
even more RFCy than the hwprobe proposal...
The first three patches have been posted previously by their respective
authors and are currently under active review (except patch2 which
appears to have gotten lost in the shuffle). I've collected these
patches into the series since they're necessary for the base and
because I wanted to repost patch2 and patch3 with some changes. patch4
and patch6 expose more extensions to userspace. patch9 adds a consistency
test for the new hwprobe base behavior bit.
Thanks,
drew
Andrew Jones (8):
riscv: Add B to hwcap
riscv: hwprobe.rst: Replace tabs with spaces
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe
riscv: Export have_user_pmlen* booleans
riscv: hwprobe: Introduce rva23u64 base behavior
riscv: selftests: hwprobe: Check rva23u64 consistency
riscv: /proc/cpuinfo: Add rva23 bases to output
riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases
Charlie Jenkins (1):
riscv: Standardize extension capitilization
Jesse Taube (1):
RISC-V: Add Zicclsm to cpufeature and hwprobe
Paul Walmsley (1):
riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1
Documentation/arch/riscv/hwprobe.rst | 42 ++-
arch/riscv/include/asm/cpufeature.h | 14 +
arch/riscv/include/asm/hwcap.h | 23 +-
arch/riscv/include/asm/hwprobe.h | 3 +-
arch/riscv/include/asm/switch_to.h | 4 +-
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/hwprobe.h | 9 +-
arch/riscv/kernel/cpu.c | 38 +++
arch/riscv/kernel/cpufeature.c | 168 ++++++++++--
arch/riscv/kernel/process.c | 12 +-
arch/riscv/kernel/sys_hwprobe.c | 249 +++++++++++++-----
arch/riscv/kvm/main.c | 2 +-
arch/riscv/kvm/vcpu_fp.c | 28 +-
arch/riscv/kvm/vcpu_onereg.c | 22 +-
arch/riscv/kvm/vcpu_vector.c | 14 +-
.../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++-
.../selftests/riscv/hwprobe/which-cpus.c | 20 +-
17 files changed, 610 insertions(+), 151 deletions(-)
--
2.43.0
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