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Message-ID: <54c65bad972e792a4e8c27b79d3c0b58596f5ab0.camel@nvidia.com>
Date: Fri, 6 Feb 2026 18:07:27 +0000
From: Timur Tabi <ttabi@...dia.com>
To: Alexandre Courbot <acourbot@...dia.com>, "dakr@...nel.org"
<dakr@...nel.org>, John Hubbard <jhubbard@...dia.com>
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Subject: Re: [PATCH v3 16/30] gpu: nova-core: Hopper/Blackwell: add FSP falcon
EMEM operations
On Thu, 2026-02-05 at 20:21 -0800, John Hubbard wrote:
> +/// EMEM control register bit 24: write mode.
> +const EMEM_CTL_WRITE: u32 = 1 << 24;
> +/// EMEM control register bit 25: read mode.
> +const EMEM_CTL_READ: u32 = 1 << 25;
> +
Shouldn't these be bits in the NV_PFALCON_FALCON_EMEM_CTL register instead?
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