linux-kernel - Re: [PATCH] x86/cpufeatures: Add AVX512 Bit Matrix Multiply (BMM) and Bit reversal support

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Message-ID: <714e7541-7bc1-4087-b780-49cb9a52bc69@amd.com>
Date: Fri, 6 Feb 2026 09:00:56 +0530
From: "Nikunj A. Dadhania" <nikunj@....com>
To: Sean Christopherson <seanjc@...gle.com>
CC: <pbonzini@...hat.com>, <bp@...en8.de>, <x86@...nel.org>,
	<babu.moger@....com>, <linux-kernel@...r.kernel.org>, <kvm@...r.kernel.org>,
	<thomas.lendacky@....com>, <santosh.shukla@....com>
Subject: Re: [PATCH] x86/cpufeatures: Add AVX512 Bit Matrix Multiply (BMM) and
 Bit reversal support



On 2/5/2026 8:40 PM, Sean Christopherson wrote:
> KVM: x86: Advertise AVX512 Bit Matrix Multiply (BMM) to userspace
> 
> Because the primary focus of the change is quite clearly to add KVM support,
> not to simply define the feature flag.

Sure, will update.

> 
> On Thu, Feb 05, 2026, Nikunj A Dadhania wrote:
>> Add support for AVX512 Bit Matrix Multiply (BMM) and Bit Reversal
>> instructions, a feature that enables bit matrix multiply operations and
>> bit reversal, which is exposed via CPUID leaf 0x80000021_EAX[23].
>>
>> Expose the support to guests when available by including it in the CPUID
> 
> Advertise to userspace.  The VMM decides whether or not to enumerate features to
> guests.

Ack.

Regards
Nikunj

> 
>> leaf 0x80000021_EAX feature list.
>>
>> While at it, reorder PREFETCHI to match the bit position order in CPUID
>> leaf 0x80000021_EAX for better organization.
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@....com>
>> ---
>>
>> AMD64 Bit Matrix Multiply and Bit Reversal Instructions
>> Publication #69192 Revision: 1.00
>> Issue Date: January 2026
>>
>> https://docs.amd.com/v/u/en-US/69192-PUB
>> ---
>>  arch/x86/include/asm/cpufeatures.h | 1 +
>>  arch/x86/kvm/cpuid.c               | 3 ++-
>>  2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index c3b53beb1300..2f1583c4bdc0 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -472,6 +472,7 @@
>>  #define X86_FEATURE_GP_ON_USER_CPUID	(20*32+17) /* User CPUID faulting */
>>  
>>  #define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */
>> +#define X86_FEATURE_AVX512_BMM		(20*32+23) /* AVX512 Bit Matrix Multiply instructions */
>>  #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
>>  #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
>>  #define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 88a5426674a1..b36e8f10f509 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
>> @@ -1218,11 +1218,12 @@ void kvm_set_cpu_caps(void)
>>  		F(NULL_SEL_CLR_BASE),
>>  		/* UpperAddressIgnore */
>>  		F(AUTOIBRS),
>> -		F(PREFETCHI),
>>  		EMULATED_F(NO_SMM_CTL_MSR),
>>  		/* PrefetchCtlMsr */
>>  		/* GpOnUserCpuid */
>>  		/* EPSF */
>> +		F(PREFETCHI),
>> +		F(AVX512_BMM),
>>  		SYNTHESIZED_F(SBPB),
>>  		SYNTHESIZED_F(IBPB_BRTYPE),
>>  		SYNTHESIZED_F(SRSO_NO),
>>
>> base-commit: e89f0e9a0a007e8c3afb8ecd739c0b3255422b00
>> -- 
>> 2.48.1
>>