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Message-ID: <20260206002349.96740-7-andrew.jones@oss.qualcomm.com>
Date: Thu, 5 Feb 2026 18:23:44 -0600
From: Andrew Jones <andrew.jones@....qualcomm.com>
To: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
kvm-riscv@...ts.infradead.org
Cc: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
Clément Léger <cleger@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Guodong Xu <guodong@...cstar.com>,
Charlie Jenkins <charlie@...osinc.com>,
Charlie Jenkins <thecharlesjenkins@...il.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: [RFC PATCH v1 06/11] riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe
Ziccrse is already present in cpufeature.
Signed-off-by: Andrew Jones <andrew.jones@....qualcomm.com>
---
Documentation/arch/riscv/hwprobe.rst | 16 ++++++++++++++++
arch/riscv/include/asm/hwcap.h | 3 +++
arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++
arch/riscv/kernel/cpufeature.c | 3 +++
arch/riscv/kernel/sys_hwprobe.c | 7 +++++--
5 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 4484f2a7f798..97226b7c5936 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -395,3 +395,19 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
extensions that are compatible with the
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICCAMOA`: The Ziccamoa extension is supported,
+ as defined in the RISC-V Profiles specification starting from commit
+ b1d80660 ("Updated to ratified state.")
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension is supported,
+ as defined in the RISC-V Profiles specification starting from commit
+ b1d80660 ("Updated to ratified state.")
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICCRSE`: The Ziccrse extension is supported,
+ as defined in the RISC-V Profiles specification starting from commit
+ b1d80660 ("Updated to ratified state.")
+
+ * :c:macro:`RISCV_HWPROBE_EXT_ZA64RS`: The Za64rs extension is supported,
+ as defined in the RISC-V Profiles specification starting from commit
+ b1d80660 ("Updated to ratified state.")
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index c17e11caca83..8e764dbc7413 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -112,6 +112,9 @@
#define RISCV_ISA_EXT_ZILSD 102
#define RISCV_ISA_EXT_ZCLSD 103
#define RISCV_ISA_EXT_ZICCLSM 104
+#define RISCV_ISA_EXT_ZICCAMOA 105
+#define RISCV_ISA_EXT_ZICCIF 106
+#define RISCV_ISA_EXT_ZA64RS 107
#define RISCV_ISA_EXT_XLINUXENVCFG 127
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 6a0163b54718..fed9ea6fd2b5 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -115,6 +115,10 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14
#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15
#define RISCV_HWPROBE_KEY_IMA_EXT_1 16
+#define RISCV_HWPROBE_EXT_ZICCAMOA (1 << 0)
+#define RISCV_HWPROBE_EXT_ZICCIF (1 << 1)
+#define RISCV_HWPROBE_EXT_ZICCRSE (1 << 2)
+#define RISCV_HWPROBE_EXT_ZA64RS (1 << 3)
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index ca7a34f66738..b001e78eecf6 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -488,6 +488,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
+ __RISCV_ISA_EXT_DATA(ziccamoa, RISCV_ISA_EXT_ZICCAMOA),
+ __RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),
__RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
__RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
@@ -498,6 +500,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
+ __RISCV_ISA_EXT_DATA(za64rs, RISCV_ISA_EXT_ZA64RS),
__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 76e673ab42a5..31d222301bf0 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -196,7 +196,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
* doesn't have.
*/
for_each_cpu(cpu, cpus) {
- /* struct riscv_isainfo *isainfo = &hart_isa[cpu]; */
+ struct riscv_isainfo *isainfo = &hart_isa[cpu];
/*
* Only use EXT_KEY() for extensions which can be
@@ -204,7 +204,10 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
* configuration, as no other checks, besides presence
* in the hart_isa bitmap, are made.
*/
- /* Nothing here yet */
+ EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing);
+ EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
+ EXT_KEY(isainfo->isa, ZICCRSE, pair->value, missing);
+ EXT_KEY(isainfo->isa, ZA64RS, pair->value, missing);
}
/* Now turn off reporting features if any CPU is missing it. */
--
2.43.0
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