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Message-ID: <20260206002349.96740-11-andrew.jones@oss.qualcomm.com>
Date: Thu, 5 Feb 2026 18:23:48 -0600
From: Andrew Jones <andrew.jones@....qualcomm.com>
To: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
kvm-riscv@...ts.infradead.org
Cc: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
Clément Léger <cleger@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Guodong Xu <guodong@...cstar.com>,
Charlie Jenkins <charlie@...osinc.com>,
Charlie Jenkins <thecharlesjenkins@...il.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: [RFC PATCH v1 10/11] riscv: /proc/cpuinfo: Add rva23 bases to output
Output the rva23(u|s)64 ISA bases that the ISA extensions provide on
new 'isa bases' lines both for the LCD of all harts and per hart, as
shown in the example output below when booting qemu with
-cpu rva23s64,sv39=on,pmp=on:
processor : 0
hart : 4
isa bases : rv64ima rva23u64
isa : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
mmu : sv39
mvendorid : 0x0
marchid : 0x0
mimpid : 0x0
hart isa bases : rv64ima rva23u64
hart isa : rv64imafdcbvh_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_zkt_zvbb_zve32f_zve32x_zve64d_zve64f_zve64x_zvfhmin_zvkb_zvkt_smaia_smnpm_smstateen_ssaia_sscofpmf_ssnpm_sstc_svade_svinval_svnapot_svpbmt
Signed-off-by: Andrew Jones <andrew.jones@....qualcomm.com>
---
arch/riscv/include/asm/cpufeature.h | 10 ++++
arch/riscv/kernel/cpu.c | 34 ++++++++++++
arch/riscv/kernel/cpufeature.c | 83 +++++++++++++++++++++++++++++
3 files changed, 127 insertions(+)
diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 62837fa981e8..e750735c5686 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -25,7 +25,15 @@ struct riscv_cpuinfo {
unsigned long mimpid;
};
+enum {
+ RISCV_ISA_BASE_IMA,
+ RISCV_ISA_BASE_RVA23U64,
+ RISCV_ISA_BASE_RVA23S64,
+ RISCV_NR_ISA_BASES,
+};
+
struct riscv_isainfo {
+ DECLARE_BITMAP(isa_bases, RISCV_NR_ISA_BASES);
DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
};
@@ -152,4 +160,6 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi
return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
}
+void riscv_set_isa_bases(unsigned long *isa_bases, const unsigned long *isa_bitmap);
+
#endif
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3dbc8cc557dd..228867d7dc00 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -305,6 +305,34 @@ static void print_mmu(struct seq_file *f)
seq_printf(f, "mmu\t\t: %s\n", sv_type);
}
+static DECLARE_BITMAP(riscv_isa_bases, RISCV_NR_ISA_BASES);
+
+static const char * const riscv_isa_base_names[] = {
+#ifdef CONFIG_32BIT
+ [RISCV_ISA_BASE_IMA] = "rv32ima",
+#else
+ [RISCV_ISA_BASE_IMA] = "rv64ima",
+#endif
+ [RISCV_ISA_BASE_RVA23U64] = "rva23u64",
+ [RISCV_ISA_BASE_RVA23S64] = "rva23s64",
+};
+
+static void print_isa_bases(struct seq_file *m,
+ const unsigned long *isa_bases,
+ const unsigned long *isa)
+{
+ unsigned int i;
+
+ if (bitmap_empty(isa_bases, RISCV_NR_ISA_BASES))
+ riscv_set_isa_bases((unsigned long *)isa_bases, isa);
+
+ for (i = 0; i < RISCV_NR_ISA_BASES; i++) {
+ if (test_bit(i, isa_bases))
+ seq_printf(m, " %s", riscv_isa_base_names[i]);
+ }
+ seq_puts(m, "\n");
+}
+
static void *c_start(struct seq_file *m, loff_t *pos)
{
if (*pos == nr_cpu_ids)
@@ -336,6 +364,9 @@ static int c_show(struct seq_file *m, void *v)
seq_printf(m, "processor\t: %lu\n", cpu_id);
seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
+ seq_puts(m, "isa bases\t:");
+ print_isa_bases(m, riscv_isa_bases, NULL);
+
/*
* For historical raisins, the isa: line is limited to the lowest common
* denominator of extensions supported across all harts. A true list of
@@ -360,6 +391,9 @@ static int c_show(struct seq_file *m, void *v)
seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
+ seq_puts(m, "hart isa bases\t:");
+ print_isa_bases(m, hart_isa[cpu_id].isa_bases, hart_isa[cpu_id].isa);
+
/*
* Print the ISA extensions specific to this hart, which may show
* additional extensions not present across all harts.
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b001e78eecf6..07a42545e9e0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -1262,3 +1262,86 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
}
}
#endif
+
+extern bool riscv_have_user_pmlen_7;
+
+void riscv_set_isa_bases(unsigned long *bases, const unsigned long *isa_bitmap)
+{
+ const unsigned long *isa = isa_bitmap ? isa_bitmap : riscv_isa;
+ DECLARE_BITMAP(ext_mask, RISCV_ISA_EXT_MAX) = { 0 };
+ DECLARE_BITMAP(tmp, RISCV_ISA_EXT_MAX);
+
+ /* IMA */
+ set_bit(RISCV_ISA_EXT_I, ext_mask);
+ set_bit(RISCV_ISA_EXT_M, ext_mask);
+ set_bit(RISCV_ISA_EXT_A, ext_mask);
+
+ if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+ return;
+
+ set_bit(RISCV_ISA_BASE_IMA, bases);
+
+ /* RVA23U64 */
+
+ /* Zic64b and Supm with PMLEN=7 */
+ if (riscv_cbom_block_size != 64 ||
+ riscv_cbop_block_size != 64 ||
+ riscv_cboz_block_size != 64 ||
+ !riscv_have_user_pmlen_7)
+ return;
+
+ set_bit(RISCV_ISA_EXT_F, ext_mask);
+ set_bit(RISCV_ISA_EXT_D, ext_mask);
+ set_bit(RISCV_ISA_EXT_C, ext_mask);
+ set_bit(RISCV_ISA_EXT_B, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICSR, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICNTR, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZIHPM, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICCIF, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICCRSE, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICCAMOA, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICCLSM, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZA64RS, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZIHINTPAUSE, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICBOM, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICBOP, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICBOZ, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZFHMIN, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZKT, ext_mask);
+ set_bit(RISCV_ISA_EXT_V, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZVFHMIN, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZVBB, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZVKT, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZIHINTNTL, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZICOND, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZIMOP, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZCMOP, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZCB, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZFA, ext_mask);
+ set_bit(RISCV_ISA_EXT_ZAWRS, ext_mask);
+ set_bit(RISCV_ISA_EXT_SUPM, ext_mask);
+
+ if (bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+ return;
+
+ set_bit(RISCV_ISA_BASE_RVA23U64, bases);
+
+ /* RVA23S64 */
+ set_bit(RISCV_ISA_EXT_ZIFENCEI, ext_mask);
+ /* TODO: Ss1p13 */
+ /* Svbare, Sv39 -- assumed */
+ set_bit(RISCV_ISA_EXT_SVADE, ext_mask);
+ /* TODO: Ssccptr, Sstvecd, Sstvala, Sscounterenw */
+ set_bit(RISCV_ISA_EXT_SVPBMT, ext_mask);
+ set_bit(RISCV_ISA_EXT_SVINVAL, ext_mask);
+ set_bit(RISCV_ISA_EXT_SVNAPOT, ext_mask);
+ set_bit(RISCV_ISA_EXT_SSTC, ext_mask);
+ set_bit(RISCV_ISA_EXT_SSCOFPMF, ext_mask);
+ set_bit(RISCV_ISA_EXT_SSNPM, ext_mask);
+ /* TODO: Ssu64xl */
+ /* TODO: Sha = Ssstateen, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, Shgatpa */
+ set_bit(RISCV_ISA_EXT_H, ext_mask);
+
+ if (/*TODO*/ false && !bitmap_andnot(tmp, ext_mask, isa, RISCV_ISA_EXT_MAX))
+ set_bit(RISCV_ISA_BASE_RVA23S64, bases);
+}
--
2.43.0
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