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Message-ID:
 <TY3PR01MB1134677AAAADBE00CE3328D4C8666A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Fri, 6 Feb 2026 11:49:30 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Thomas Gleixner <tglx@...nel.org>, biju.das.au <biju.das.au@...il.com>,
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Geert Uytterhoeven
	<geert+renesas@...der.be>, magnus.damm <magnus.damm@...il.com>
CC: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	biju.das.au <biju.das.au@...il.com>
Subject: RE: [PATCH v3 0/9] Add RZ/G3L IRQC support

Hi Thomas Gleixner,

Thanks for the feedback.

> -----Original Message-----
> From: Thomas Gleixner <tglx@...nel.org>
> Sent: 06 February 2026 11:38
> Subject: Re: [PATCH v3 0/9] Add RZ/G3L IRQC support
> 
> On Fri, Feb 06 2026 at 11:16, Biju wrote:
> > From: Biju Das <biju.das.jz@...renesas.com>
> >
> > The IRQC block on RZ/G3L SoC is almost identical to one found on the
> > RZ/G3S SoC with the difference like it support more External IRQs, GPT
> > Error Interrupts and also has additional registers for GPT/MTU IRQ
> > selection, shared IRQ selection between external IRQ and TINT.
> >
> > It has 16 external interrupts of which 8 interrupts are shared with
> > TINT[24:31] and are mutually exclusive. The external IRQ/TINT IRQ
> > selection is based on a register in the ICU block.
> 
> Can you please give people the time to actually look at your patches before you repost the full series
> every other day?

Sorry for that. Will take care next time.

Thanks,
Biju


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