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Message-ID:
<MW5PR12MB5681FAEA87806E8BACF7B8C8A067A@MW5PR12MB5681.namprd12.prod.outlook.com>
Date: Sat, 7 Feb 2026 00:27:39 +0000
From: Besar Wicaksono <bwicaksono@...dia.com>
To: James Clark <james.clark@...aro.org>, Ian Rogers <irogers@...gle.com>
CC: "john.g.garry@...cle.com" <john.g.garry@...cle.com>, "will@...nel.org"
<will@...nel.org>, "mike.leach@...aro.org" <mike.leach@...aro.org>,
"leo.yan@...ux.dev" <leo.yan@...ux.dev>, "mark.rutland@....com"
<mark.rutland@....com>, "alexander.shishkin@...ux.intel.com"
<alexander.shishkin@...ux.intel.com>, "jolsa@...nel.org" <jolsa@...nel.org>,
"adrian.hunter@...el.com" <adrian.hunter@...el.com>, "peterz@...radead.org"
<peterz@...radead.org>, "mingo@...hat.com" <mingo@...hat.com>,
"acme@...nel.org" <acme@...nel.org>, "namhyung@...nel.org"
<namhyung@...nel.org>, "linux-tegra@...r.kernel.org"
<linux-tegra@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-perf-users@...r.kernel.org"
<linux-perf-users@...r.kernel.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, Thomas Makin <tmakin@...dia.com>, Vikram
Sethi <vsethi@...dia.com>, Rich Wiley <rwiley@...dia.com>, Sean Kelley
<skelley@...dia.com>, Yifei Wan <YWan@...dia.com>, Thierry Reding
<treding@...dia.com>, Jon Hunter <jonathanh@...dia.com>, Matt Ochs
<mochs@...dia.com>
Subject: RE: [PATCH] perf vendor events arm64: Add Tegra410 Olympus PMU events
> -----Original Message-----
> From: James Clark <james.clark@...aro.org>
> Sent: Monday, February 2, 2026 3:59 AM
> To: Besar Wicaksono <bwicaksono@...dia.com>; Ian Rogers
> <irogers@...gle.com>
> Cc: john.g.garry@...cle.com; will@...nel.org; mike.leach@...aro.org;
> leo.yan@...ux.dev; mark.rutland@....com;
> alexander.shishkin@...ux.intel.com; jolsa@...nel.org;
> adrian.hunter@...el.com; peterz@...radead.org; mingo@...hat.com;
> acme@...nel.org; namhyung@...nel.org; linux-tegra@...r.kernel.org; linux-
> arm-kernel@...ts.infradead.org; linux-perf-users@...r.kernel.org; linux-
> kernel@...r.kernel.org; Thomas Makin <tmakin@...dia.com>; Vikram Sethi
> <vsethi@...dia.com>; Rich Wiley <rwiley@...dia.com>; Sean Kelley
> <skelley@...dia.com>; Yifei Wan <YWan@...dia.com>; Thierry Reding
> <treding@...dia.com>; Jon Hunter <jonathanh@...dia.com>; Matt Ochs
> <mochs@...dia.com>
> Subject: Re: [PATCH] perf vendor events arm64: Add Tegra410 Olympus PMU
> events
>
> External email: Use caution opening links or attachments
>
>
> On 30/01/2026 6:08 pm, Besar Wicaksono wrote:
> > Thank you James and Ian for the comments.
> > I will try to address the spelling mistakes on v2.
> >
> > Please see my other comments inline.
> >
> >> -----Original Message-----
> >> From: James Clark <james.clark@...aro.org>
> >> Sent: Wednesday, January 28, 2026 3:37 AM
> >> To: Ian Rogers <irogers@...gle.com>; Besar Wicaksono
> >> <bwicaksono@...dia.com>
> >> Cc: john.g.garry@...cle.com; will@...nel.org; mike.leach@...aro.org;
> >> leo.yan@...ux.dev; mark.rutland@....com;
> >> alexander.shishkin@...ux.intel.com; jolsa@...nel.org;
> >> adrian.hunter@...el.com; peterz@...radead.org; mingo@...hat.com;
> >> acme@...nel.org; namhyung@...nel.org; linux-tegra@...r.kernel.org;
> linux-
> >> arm-kernel@...ts.infradead.org; linux-perf-users@...r.kernel.org; linux-
> >> kernel@...r.kernel.org; Thomas Makin <tmakin@...dia.com>; Vikram
> Sethi
> >> <vsethi@...dia.com>; Rich Wiley <rwiley@...dia.com>; Sean Kelley
> >> <skelley@...dia.com>; Yifei Wan <ywan@...dia.com>; Thierry Reding
> >> <treding@...dia.com>; Jon Hunter <jonathanh@...dia.com>; Matt Ochs
> >> <mochs@...dia.com>
> >> Subject: Re: [PATCH] perf vendor events arm64: Add Tegra410 Olympus
> PMU
> >> events
> >>
> >> External email: Use caution opening links or attachments
> >>
> >>
> >> On 28/01/2026 8:03 am, Ian Rogers wrote:
> >>> On Tue, Jan 27, 2026 at 3:00 PM Besar Wicaksono
> >> <bwicaksono@...dia.com> wrote:
> >>>>
> >>>> Add JSON files for NVIDIA Tegra410 Olympus core PMU events.
> >>>> Also updated the common-and-microarch.json.
> >>>>
> >>>> Signed-off-by: Besar Wicaksono <bwicaksono@...dia.com>
> >>>> ---
> >>>> .../arch/arm64/common-and-microarch.json | 90 +++
> >>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 +
> >>>> .../arch/arm64/nvidia/t410/branch.json | 45 ++
> >>>> .../arch/arm64/nvidia/t410/brbe.json | 6 +
> >>>> .../arch/arm64/nvidia/t410/bus.json | 48 ++
> >>>> .../arch/arm64/nvidia/t410/exception.json | 62 ++
> >>>> .../arch/arm64/nvidia/t410/fp_operation.json | 78 ++
> >>>> .../arch/arm64/nvidia/t410/general.json | 15 +
> >>>> .../arch/arm64/nvidia/t410/l1d_cache.json | 122 +++
> >>>> .../arch/arm64/nvidia/t410/l1i_cache.json | 114 +++
> >>>> .../arch/arm64/nvidia/t410/l2d_cache.json | 134 ++++
> >>>> .../arch/arm64/nvidia/t410/ll_cache.json | 107 +++
> >>>> .../arch/arm64/nvidia/t410/memory.json | 46 ++
> >>>> .../arch/arm64/nvidia/t410/metrics.json | 722
> >> ++++++++++++++++++
> >>>> .../arch/arm64/nvidia/t410/misc.json | 646 ++++++++++++++++
> >>>> .../arch/arm64/nvidia/t410/retired.json | 94 +++
> >>>> .../arch/arm64/nvidia/t410/spe.json | 42 +
> >>>> .../arm64/nvidia/t410/spec_operation.json | 230 ++++++
> >>>> .../arch/arm64/nvidia/t410/stall.json | 145 ++++
> >>>> .../arch/arm64/nvidia/t410/tlb.json | 158 ++++
> >>>> 20 files changed, 2905 insertions(+)
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/branch.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/brbe.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/bus.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/exception.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/fp_operation.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/general.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/l1d_cache.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/l1i_cache.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/l2d_cache.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/ll_cache.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/memory.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/metrics.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/misc.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/retired.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/spe.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/spec_operation.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/stall.json
> >>>> create mode 100644 tools/perf/pmu-
> >> events/arch/arm64/nvidia/t410/tlb.json
> >>>>
> >>>> diff --git a/tools/perf/pmu-events/arch/arm64/common-and-
> >> microarch.json b/tools/perf/pmu-events/arch/arm64/common-and-
> >> microarch.json
> >>>> index 468cb085d879..6af15776ff17 100644
> >>>> --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json
> >>>> +++ b/tools/perf/pmu-events/arch/arm64/common-and-
> microarch.json
> >>>> @@ -179,6 +179,11 @@
> >>>> "EventName": "BUS_CYCLES",
> >>>> "BriefDescription": "Bus cycle"
> >>>> },
> >>>> + {
> >>>> + "EventCode": "0x001E",
> >>>> + "EventName": "CHAIN",
> >>>> + "BriefDescription": "Chain a pair of event counters."
> >>>> + },
> >>>
> >>> Cool stuff :-)
> >>>
> >>> For wider counters AMD does something similar, but should this be an
> >>> implementation detail rather than an exposed event? How does it
> >>> operate as an event?
> >>>
> >>
> >> CHAIN should be excluded from the json, it's used internally by the
> >> driver when you want 64 bit counters. Userspace can't use it because it
> >> can't control where counters are placed to make sure they're adjacent.
> >>
> >
> > Sure, will address this in V2.
> >
> >>> [snip]
> >>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> >> b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> >>>> index bb3fa8a33496..7f0eaa702048 100644
> >>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv
> >>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> >>>> @@ -46,3 +46,4 @@
> >>>> 0x00000000500f0000,v1,ampere/emag,core
> >>>> 0x00000000c00fac30,v1,ampere/ampereone,core
> >>>> 0x00000000c00fac40,v1,ampere/ampereonex,core
> >>>> +0x000000004e0f0100,v1,nvidia/t410,core
> >>>> diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json
> >> b/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json
> >>>> new file mode 100644
> >>>> index 000000000000..532bc59dc573
> >>>> --- /dev/null
> >>>> +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json
> >>>> @@ -0,0 +1,45 @@
> >>>> +[
> >>>> + {
> >>>> + "ArchStdEvent": "BR_MIS_PRED",
> >>>> + "PublicDescription": "The Event counts Branches which are
> >> speculatively executed and mis-predicted."
> >>>
> >>> nit: The capitalization on Event and Branches, as well as other words,
> >>> is a little unusual.
> >>>
> >>
> >> If there's nothing specific to this CPU then the public description
> >> could be left out entierly. The common strings already say the same
> >> thing as this:
> >>
> >> {
> >> "PublicDescription": "Mispredicted or not predicted branch
> >> speculatively executed",
> >> "EventCode": "0x10",
> >> "EventName": "BR_MIS_PRED",
> >> "BriefDescription": "Mispredicted or not predicted branch
> >> speculatively executed"
> >> },
> >>
> >>
> >
> > I will check on this and other events.
James, on a second thought, the description of the events was imported from
Olympus TRM. So just to keep my import flow simpler, if there is no major
concern, I would prefer to keep the description as is.
Thanks
Besar
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