linux-kernel - [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm

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Message-Id: <20260207-isa-ext-parse-export-v1-4-a64d3a8bc20a@riscstar.com>
Date: Sat, 07 Feb 2026 18:27:58 +0800
From: Guodong Xu <guodong@...cstar.com>
To: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, 
 Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, 
 Jonathan Corbet <corbet@....net>, Shuah Khan <skhan@...uxfoundation.org>, 
 Conor Dooley <conor@...nel.org>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 linux-doc@...r.kernel.org, Guodong Xu <guodong@...cstar.com>
Subject: [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa,
 Ziccif, and Zicclsm

Add ISA extension parsing for four memory system related extensions:

 - Za64rs: reservation set size of at most 64 bytes
 - Ziccamoa: main memory must support all atomics in A
 - Ziccif: main memory instruction fetch atomicity
 - Zicclsm: main memory must support misaligned loads and stores

Za64rs depends on Zalrsc (or the A extension, which implies Zalrsc).
Ziccamoa depends on Zaamo (or the A extension, which implies Zaamo).
Both use dependency callbacks to enforce these requirements.

All of them are labeled as mandatory in RVA23 Profile 1.0.

Signed-off-by: Guodong Xu <guodong@...cstar.com>
---
 arch/riscv/include/asm/hwcap.h |  4 ++++
 arch/riscv/kernel/cpufeature.c | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759..5a050fae5302c7717596799967d8d514e7dfc536 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -114,6 +114,10 @@
 #define RISCV_ISA_EXT_ZICFILP		104
 #define RISCV_ISA_EXT_ZICFISS		105
 #define RISCV_ISA_EXT_SUPM		106
+#define RISCV_ISA_EXT_ZA64RS		107
+#define RISCV_ISA_EXT_ZICCAMOA		108
+#define RISCV_ISA_EXT_ZICCIF		109
+#define RISCV_ISA_EXT_ZICCLSM		110
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 68c94fe29cd1b26925fa38a5c877d699bbc88e25..fee5b20bb171334e8ca60af25485f43a9acef619 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -347,6 +347,15 @@ static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data,
 	return -EPROBE_DEFER;
 }
 
+static int riscv_ext_zaamo_depends(const struct riscv_isa_ext_data *data,
+				   const unsigned long *isa_bitmap)
+{
+	if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZAAMO))
+		return 0;
+
+	return -EPROBE_DEFER;
+}
+
 static const unsigned int riscv_a_exts[] = {
 	RISCV_ISA_EXT_ZAAMO,
 	RISCV_ISA_EXT_ZALRSC,
@@ -552,6 +561,9 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
+	__RISCV_ISA_EXT_DATA_VALIDATE(ziccamoa, RISCV_ISA_EXT_ZICCAMOA, riscv_ext_zaamo_depends),
+	__RISCV_ISA_EXT_DATA(ziccif, RISCV_ISA_EXT_ZICCIF),
+	__RISCV_ISA_EXT_DATA(zicclsm, RISCV_ISA_EXT_ZICCLSM),
 	__RISCV_ISA_EXT_DATA_VALIDATE(ziccrse, RISCV_ISA_EXT_ZICCRSE, riscv_ext_zalrsc_depends),
 	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts,
 					  riscv_cfilp_validate),
@@ -565,6 +577,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP),
+	__RISCV_ISA_EXT_DATA_VALIDATE(za64rs, RISCV_ISA_EXT_ZA64RS, riscv_ext_zalrsc_depends),
 	__RISCV_ISA_EXT_DATA(zaamo, RISCV_ISA_EXT_ZAAMO),
 	__RISCV_ISA_EXT_DATA(zabha, RISCV_ISA_EXT_ZABHA),
 	__RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS),

-- 
2.43.0