linux-kernel - [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl

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Message-Id: <20260207-isa-ext-parse-export-v1-7-a64d3a8bc20a@riscstar.com>
Date: Sat, 07 Feb 2026 18:28:01 +0800
From: Guodong Xu <guodong@...cstar.com>
To: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, 
 Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, 
 Jonathan Corbet <corbet@....net>, Shuah Khan <skhan@...uxfoundation.org>, 
 Conor Dooley <conor@...nel.org>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
 linux-doc@...r.kernel.org, Guodong Xu <guodong@...cstar.com>
Subject: [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr,
 Sscounterenw, Sstvala, Sstvecd, and Ssu64xl

Add ISA extension parsing for five supervisor-level extensions ratified
in RISC-V Profiles Version 1.0:

 - Ssccptr: main memory hardware page-table reads
 - Sscounterenw: writable enables in scounteren for any supported counter
 - Sstvala: stval provides all needed values
 - Sstvecd: stvec supports Direct mode
 - Ssu64xl: UXLEN=64 must be supported

These are simple extensions with no dependencies.

All of them are labeled as mandatory in RVA23 Profile 1.0.

Signed-off-by: Guodong Xu <guodong@...cstar.com>
---
 arch/riscv/include/asm/hwcap.h | 5 +++++
 arch/riscv/kernel/cpufeature.c | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5a050fae5302c7717596799967d8d514e7dfc536..75f64f5b7355db6ea5218f544ceda3be9619a58a 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -118,6 +118,11 @@
 #define RISCV_ISA_EXT_ZICCAMOA		108
 #define RISCV_ISA_EXT_ZICCIF		109
 #define RISCV_ISA_EXT_ZICCLSM		110
+#define RISCV_ISA_EXT_SSCCPTR		111
+#define RISCV_ISA_EXT_SSCOUNTERENW	112
+#define RISCV_ISA_EXT_SSTVALA		113
+#define RISCV_ISA_EXT_SSTVECD		114
+#define RISCV_ISA_EXT_SSU64XL		115
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fee5b20bb171334e8ca60af25485f43a9acef619..fff35a3e85db70f5610df2667f2b4f45f091cb2b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -643,9 +643,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
+	__RISCV_ISA_EXT_DATA(ssccptr, RISCV_ISA_EXT_SSCCPTR),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+	__RISCV_ISA_EXT_DATA(sscounterenw, RISCV_ISA_EXT_SSCOUNTERENW),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
+	__RISCV_ISA_EXT_DATA(sstvala, RISCV_ISA_EXT_SSTVALA),
+	__RISCV_ISA_EXT_DATA(sstvecd, RISCV_ISA_EXT_SSTVECD),
+	__RISCV_ISA_EXT_DATA(ssu64xl, RISCV_ISA_EXT_SSU64XL),
 	__RISCV_ISA_EXT_DATA_VALIDATE(supm, RISCV_ISA_EXT_SUPM, riscv_ext_supm_validate),
 	__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
 	__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),

-- 
2.43.0