[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20260207-armored-diligent-grasshopper-b58d3f@quoll>
Date: Sat, 7 Feb 2026 11:44:53 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Judith Mendez <jm@...com>
Cc: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Santosh Shilimkar <ssantosh@...nel.org>, linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Andrew Davis <afd@...com>
Subject: Re: [PATCH v2 1/2] dt-bindings: hwinfo: ti,k3-socinfo: Add
nvmem-cells support
On Fri, Feb 06, 2026 at 01:19:13PM -0600, Judith Mendez wrote:
> Add optional nvmem-cells and nvmem-cell-names properties to support
> reading silicon revision information from alternate location using
> NVMEM providers. This is used on AM62P to read GP_SW1 register for
> accurate silicon revision detection.
>
> Signed-off-by: Judith Mendez <jm@...com>
> ---
> Changes since v1:
> - no change
> ---
> .../devicetree/bindings/hwinfo/ti,k3-socinfo.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> index dada28b47ea07..58cc937e13351 100644
> --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml
> @@ -15,6 +15,9 @@ description: |
> represented by CTRLMMR_xxx_JTAGID register which contains information about
> SoC id and revision.
>
> + On some SoCs like AM62P, the silicon revision is determined by reading
> + alternative registers via NVMEM cells.
> +
> properties:
> $nodename:
> pattern: "^chipid@[0-9a-f]+$"
> @@ -26,6 +29,15 @@ properties:
> reg:
> maxItems: 1
>
> + nvmem-cells:
> + maxItems: 1
> + description:
> + Reference to NVMEM node containing revision information.
Intead items with description. And drop 'Reference to NVMEM node
containing', redundant. Just say what NVMEM it is supposed to be.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@....qualcomm.com>
Best regards,
Krzysztof
Powered by blists - more mailing lists