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Message-ID:
<VI0PR04MB121144CB5409498A2B52B2D669267A@VI0PR04MB12114.eurprd04.prod.outlook.com>
Date: Sat, 7 Feb 2026 03:29:25 +0000
From: Sherry Sun <sherry.sun@....com>
To: Hongxing Zhu <hongxing.zhu@....com>, "robh@...nel.org" <robh@...nel.org>,
"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
<conor+dt@...nel.org>, "shawnguo@...nel.org" <shawnguo@...nel.org>, Frank Li
<frank.li@....com>, "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>
CC: "kernel@...gutronix.de" <kernel@...gutronix.de>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
<linux-kernel@...r.kernel.org>, Hongxing Zhu <hongxing.zhu@....com>
Subject: RE: [PATCH v1 3/3] arm64: dts: imx943-evk: Add pcie[0,1] and
pcie-ep[0,1] support
> Subject: [PATCH v1 3/3] arm64: dts: imx943-evk: Add pcie[0,1] and pcie-
> ep[0,1] support
>
> Add pcie[0,1] and pcie-ep[0,1] support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
> arch/arm64/boot/dts/freescale/imx943-evk.dts | 108 +++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> index 31fa9675cee13..37a8349bc7905 100644
> --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> @@ -53,6 +53,13 @@ dmic: dmic {
> #sound-dai-cells = <0>;
> };
>
> + pcie_ref_clk: clock-pcie-ref {
> + compatible = "gpio-gate-clock";
> + clocks = <&xtal25m>;
> + #clock-cells = <0>;
> + enable-gpios = <&pca9670_i2c3 7 GPIO_ACTIVE_LOW>;
> + };
> +
> reg_usdhc2_vmmc: regulator-usdhc2 {
> compatible = "regulator-fixed";
> off-on-delay-us = <12000>;
> @@ -74,6 +81,41 @@ reg_audio_pwr: regulator-wm8962-pwr {
> enable-active-high;
> };
>
> + reg_m2_pwr: regulator-m2-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "M.2-power";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pcal6416_i2c3_u46 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + /*
> + * M.2 device only can be enabled(W_DISABLE1#) after all
> Power
> + * Rails reach their minimum operating voltage (PCI Express
> M.2
> + * Specification r5.1 3.1.4 Power-up Timing).
> + * Set a delay equal to the max value of Tsettle here.
> + */
> + startup-delay-us = <5000>;
> + };
> +
> + reg_pcie0: regulator-pcie {
> + compatible = "regulator-fixed";
> + regulator-name = "PCIE_WLAN_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <®_m2_pwr>;
> + gpio = <&pcal6416_i2c3_u46 5 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
Hi Richard,
Please check the patch here: https://patchwork.kernel.org/project/imx/patch/20260204022306.2372889-1-sherry.sun@nxp.com/
I have added the reg_m2_pwr and reg_pcie0(rename to reg_m2_wlan
to support SDIO wifi), so you can delete these two nodes in your patch.
Best Regards
Sherry
> + reg_slot_pwr: regulator-slot-pwr {
> + compatible = "regulator-fixed";
> + regulator-name = "PCIe slot-power";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&pcal6416_i2c3_u46 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reserved-memory {
> ranges;
> #address-cells = <2>;
> @@ -144,6 +186,13 @@ memory@...00000 {
> reg = <0x0 0x80000000 0x0 0x80000000>;
> device_type = "memory";
> };
> +
> + xtal25m: clock-xtal25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "xtal_25MHz";
> + };
> };
>
> &enetc1 {
> @@ -609,6 +658,18 @@ IMX94_PAD_GPIO_IO28__LPI2C6_SCL
> 0x40000b9e
> >;
> };
>
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B
> 0x4000031e
> + >;
> + };
> +
> + pinctrl_pcie1: pcie1grp {
> + fsl,pins = <
> + IMX94_PAD_GPIO_IO23__PCIE2_CLKREQ_B
> 0x4000031e
> + >;
> + };
> +
> pinctrl_pdm: pdmgrp {
> fsl,pins = <
> IMX94_PAD_PDM_CLK__PDM_CLK
> 0x31e
> @@ -756,6 +817,53 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe
> };
> };
>
> +&pcie0 {
> + pinctrl-0 = <&pinctrl_pcie0>;
> + pinctrl-names = "default";
> + clocks = <&scmi_clk IMX94_CLK_HSIO>,
> + <&scmi_clk IMX94_CLK_HSIOPLL>,
> + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
> + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>,
> + <&pcie_ref_clk>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
> + "ref", "extref";
> + reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
> + vpcie3v3aux-supply = <®_pcie0>;
> + supports-clkreq;
> + status = "okay";
> +};
> +
> +&pcie0_ep {
> + pinctrl-0 = <&pinctrl_pcie0>;
> + pinctrl-names = "default";
> + vpcie3v3aux-supply = <®_pcie0>;
> + status = "disabled";
> +};
> +
> +&pcie1 {
> + pinctrl-0 = <&pinctrl_pcie1>;
> + pinctrl-names = "default";
> + clocks = <&scmi_clk IMX94_CLK_HSIO>,
> + <&scmi_clk IMX94_CLK_HSIOPLL>,
> + <&scmi_clk IMX94_CLK_HSIOPLL_VCO>,
> + <&scmi_clk IMX94_CLK_HSIOPCIEAUX>,
> + <&hsio_blk_ctl 0>,
> + <&pcie_ref_clk>;
> + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
> + "ref", "extref";
> + reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
> + vpcie3v3aux-supply = <®_slot_pwr>;
> + status = "okay";
> +};
> +
> +&pcie1_ep {
> + pinctrl-0 = <&pinctrl_pcie1>;
> + pinctrl-names = "default";
> + vpcie3v3aux-supply = <®_slot_pwr>;
> + status = "disabled";
> +};
> +
> &usdhc1 {
> pinctrl-0 = <&pinctrl_usdhc1>;
> pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> --
> 2.37.1
>
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