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Message-ID: <eb423286-c26b-4e03-9e9e-af6718e459cc@kernel.org>
Date: Sun, 8 Feb 2026 10:05:08 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: webgeek1234@...il.com, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8550: add cpu interconnect nodes
On 08/02/2026 02:28, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@...il.com>
>
> Add the interconnect entry for each cpu, with 3 different paths:
> - CPU to Last Level Cache Controller (LLCC)
> - Last Level Cache Controller (LLCC) to DDR
> - L3 Cache from CPU to DDR interface
>
> Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 49 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
This patch should be squashed. You add interconnect and use it,
otherwise it is pretty pointless or even negatively impacting (syncing
without interconnect paths).
Best regards,
Krzysztof
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