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Message-ID: <aYiWA5ev2nPF8UxU@smile.fi.intel.com>
Date: Sun, 8 Feb 2026 15:56:19 +0200
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Marcelo Schmitt <marcelo.schmitt@...log.com>
Cc: linux-iio@...r.kernel.org, devicetree@...r.kernel.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
jic23@...nel.org, michael.hennerich@...log.com, nuno.sa@...log.com,
eblanc@...libre.com, dlechner@...libre.com, andy@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
corbet@....net, marcelo.schmitt1@...il.com,
Trevor Gamblin <tgamblin@...libre.com>,
Axel Haslam <ahaslam@...libre.com>
Subject: Re: [PATCH v8 5/8] iio: adc: ad4030: Add SPI offload support
On Fri, Feb 06, 2026 at 04:01:33PM -0300, Marcelo Schmitt wrote:
> AD4030 and similar ADCs can capture data at sample rates up to 2 mega
> samples per second (MSPS). Not all SPI controllers are able to achieve such
> high throughputs and even when the controller is fast enough to run
> transfers at the required speed, it may be costly to the CPU to handle
> transfer data at such high sample rates. Add SPI offload support for AD4030
> and similar ADCs to enable data capture at maximum sample rates.
...
> +static int ad4030_update_conversion_rate(struct ad4030_state *st,
> + unsigned int freq_hz, unsigned int avg_log2)
> +{
> + struct spi_offload_trigger_config *config = &st->offload_trigger_config;
> + unsigned int offload_period_ns, cnv_rate_hz;
> + struct pwm_waveform cnv_wf = { };
> + u64 target = AD4030_TCNVH_NS;
> + u64 offload_offset_ns;
> + int ret;
> +
> + /*
> + * When averaging/oversampling over N samples, we fire the offload
> + * trigger once at every N pulses of the CNV signal. Conversely, the CNV
> + * signal needs to be N times faster than the offload trigger. Take that
> + * into account to correctly re-evaluate both the PWM waveform connected
> + * to CNV and the SPI offload trigger.
> + */
> + cnv_rate_hz = freq_hz << avg_log2;
> +
> + cnv_wf.period_length_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, cnv_rate_hz);
See below.
> + /*
> + * The datasheet lists a minimum time of 9.8 ns, but no maximum. If the
> + * rounded PWM's value is less than 10, increase the target value by 10
> + * and attempt to round the waveform again, until the value is at least
> + * 10 ns. Use a separate variable to represent the target in case the
> + * rounding is severe enough to keep putting the first few results under
> + * the minimum 10ns condition checked by the while loop.
> + */
> + do {
> + cnv_wf.duty_length_ns = target;
> + ret = pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf);
> + if (ret)
> + return ret;
> + target += AD4030_TCNVH_NS;
> + } while (cnv_wf.duty_length_ns < AD4030_TCNVH_NS);
Does the above have a side-effect on period_length_ns? If not, the below check
should be moved up, otherwise here should be a short comment explaining the
side-effect(s).
> + if (!in_range(cnv_wf.period_length_ns, AD4030_TCYC_NS, INT_MAX))
> + return -EINVAL;
> + offload_period_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_hz);
> +
> + config->periodic.frequency_hz = DIV_ROUND_UP(HZ_PER_GHZ, offload_period_ns);
> +
> + /*
> + * The hardware does the capture on zone 2 (when SPI trigger PWM
> + * is used). This means that the SPI trigger signal should happen at
> + * tsync + tquiet_con_delay being tsync the conversion signal period
> + * and tquiet_con_delay 9.8ns. Hence set the PWM phase accordingly.
> + *
> + * The PWM waveform API only supports nanosecond resolution right now,
> + * so round this setting to the closest available value.
> + */
> + offload_offset_ns = AD4030_TQUIET_CNV_DELAY_NS;
> + do {
> + config->periodic.offset_ns = offload_offset_ns;
> + ret = spi_offload_trigger_validate(st->offload_trigger, config);
> + if (ret)
> + return ret;
> + offload_offset_ns += AD4030_TQUIET_CNV_DELAY_NS;
> + } while (config->periodic.offset_ns < AD4030_TQUIET_CNV_DELAY_NS);
> +
> + st->cnv_wf = cnv_wf;
> +
> + return 0;
> +}
--
With Best Regards,
Andy Shevchenko
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