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Message-ID: <3ffm2j66avwpud3sdgjua7jrkhb7bgbaxlp3jnzve7p2xpmcnj@slek5n6t54zn>
Date: Sun, 8 Feb 2026 10:15:15 -0600
From: Andrew Jones <andrew.jones@....qualcomm.com>
To: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
kvm-riscv@...ts.infradead.org
Cc: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
Clément Léger <cleger@...osinc.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Guodong Xu <guodong@...cstar.com>,
Charlie Jenkins <charlie@...osinc.com>,
Charlie Jenkins <thecharlesjenkins@...il.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: Re: [RFC PATCH v1 08/11] riscv: hwprobe: Introduce rva23u64 base
behavior
On Thu, Feb 05, 2026 at 06:23:46PM -0600, Andrew Jones wrote:
...
> +static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
> +{
> + struct riscv_hwprobe pair;
> +
> + if (!IS_ENABLED(CONFIG_64BIT))
> + return false;
> +
> + /* Additional mandates for Zic64b and Supm */
> + if (riscv_cbom_block_size != 64 ||
> + riscv_cbop_block_size != 64 ||
> + riscv_cboz_block_size != 64 ||
> + !riscv_have_user_pmlen_7)
> + return false;
> +
Thanks to kernel test robot's report I'll fix the compilation of this for
configs without RISCV_ISA_SUPM with the following change and something
similar for patch10.
Thanks,
drew
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 4b9981b15ebe..3fd63ac7dd60 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -278,7 +278,7 @@ static bool hwprobe_has_rva23u64(const struct cpumask *cpus)
if (riscv_cbom_block_size != 64 ||
riscv_cbop_block_size != 64 ||
riscv_cboz_block_size != 64 ||
- !riscv_have_user_pmlen_7)
+ !IS_ENABLED(CONFIG_RISCV_ISA_SUPM) || !riscv_have_user_pmlen_7)
return false;
hwprobe_isa_ext0(&pair, cpus);
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